diff options
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/Kconfig | 18 | ||||
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl | 8 | ||||
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/acpi/i82801db.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/dsdt.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/romstage.c | 34 |
6 files changed, 15 insertions, 52 deletions
diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index c3025d157a..da03491d87 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -8,8 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_LPC47M10X - select ROMCC - select HAVE_HARD_RESET # select HAVE_PIRQ_TABLE # select PIRQ_ROUTE select UDELAY_TSC @@ -24,14 +22,6 @@ config MAINBOARD_PART_NUMBER string default "DXPL Plus-U" -config DCACHE_RAM_BASE - hex - default 0xcf000 - -config DCACHE_RAM_SIZE - hex - default 0x1000 - config IRQ_SLOT_COUNT int default 12 @@ -40,18 +30,10 @@ config BOARD_HAS_FADT bool default y -config LOGICAL_CPUS - bool - default n - config MAX_CPUS int default 4 -config MAX_PHYSICAL_CPUS - int - default 2 - config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x0 diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl index 0effe9367d..463b6be2f1 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl @@ -44,8 +44,8 @@ Name (PBRS, ResourceTemplate () /* Top Of Lowmemory to IOAPIC */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x02000000, 0xFEBFFFFF, - 0x00000000, 0xFCC00000, ,, _Y08, AddressRangeMemory, TypeStatic) + 0x00000000, 0x00000000, 0xFEBFFFFF, + 0x00000000, IO_APIC_ADDR, ,, _Y08, AddressRangeMemory, TypeStatic) }) @@ -54,11 +54,13 @@ Method (_CRS, 0, NotSerialized) /* Top Of Lowmemory to IOAPIC */ CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML) + CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH) CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM) And (\_SB.PCI0.TOLM, 0xF800, Local1) ShiftRight (Local1, 0x04, Local1) ShiftLeft (Local1, 0x14, MEML) - Subtract (0xFEC00000, MEML, LENM) + Subtract (IO_APIC_ADDR, 0x01, MEMH) + Subtract (IO_APIC_ADDR, MEML, LENM) Return (PBRS) } diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl index bb8c3218c3..a1a23f2470 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -96,7 +96,7 @@ Device (ICH0) Name (MSBF, ResourceTemplate () { /* IOAPIC 0 */ - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000,) + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000,) IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO) IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO) diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index d465a82e7a..94a38d7f45 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -24,6 +24,7 @@ chip northbridge/intel/e7505 device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 device lapic 0 on end + device lapic 6 on end end end @@ -79,6 +80,8 @@ chip northbridge/intel/e7505 end end device pci 1f.1 on end # IDE + register "ide0_enable" = "1" + register "ide1_enable" = "1" device pci 1f.3 on end # SMBus device pci 1f.5 on end # AC97 Audio device pci 1f.6 off end # AC97 Modem diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl index 31cfa88ff3..095df060ff 100644 --- a/src/mainboard/aopen/dxplplusu/dsdt.asl +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/ioapic.h> + DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 573e0f1880..73e445b7ce 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -27,6 +27,8 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> +#include <cpu/x86/bist.h> +#include <spd.h> #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/early_smbus.c" @@ -35,13 +37,6 @@ #include "northbridge/intel/e7505/debug.c" #include "superio/smsc/lpc47m10x/early_serial.c" -#if !CONFIG_CACHE_AS_RAM -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#endif -#include "cpu/x86/bist.h" - -#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) @@ -50,21 +45,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -/* Cache-As-Ram compiles for this board, but with the CPUs I have, - * it halts on boot while in Local Apic ID negotiation. - */ - -#if CONFIG_CACHE_AS_RAM -#define BOARD_MAIN(x) void main(x) -#define early_mtrr_init() do {} while (0) -#else -#define BOARD_MAIN(x) static void main(x) -#endif - #include "northbridge/intel/e7505/raminit.c" -// This function MUST appear last (ROMCC limitation) -BOARD_MAIN(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -75,12 +58,6 @@ BOARD_MAIN(unsigned long bist) }, }; - if (bist == 0) { - // Skip this if there was a built in self test failure - early_mtrr_init(); - enable_lapic(); - } - // Get the serial port running and print a welcome banner lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -94,8 +71,5 @@ BOARD_MAIN(unsigned long bist) sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } - // NOTE: ROMCC dies with an internal compiler error - // if the following line is removed. - print_debug("SDRAM is up.\r\n"); - + print_debug("SDRAM is up.\n"); } |