diff options
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 26 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 98 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/serialio.h | 16 |
3 files changed, 109 insertions, 31 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3e4bafc322..b4d78f3cda 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2008 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,6 +36,8 @@ #include <soc/gpio_defs.h> #endif +#define SOC_INTEL_CML_UART_DEV_MAX 3 + struct soc_intel_cannonlake_config { /* Common struct containing soc config data required by common code */ @@ -101,7 +103,7 @@ struct soc_intel_cannonlake_config { * For CNL, options are as following * When enabled, memory will be training at three different frequencies. * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled - * For WHL/CFL options are as following + * For WHL/CFL/CML options are as following * When enabled, memory will be training at two different frequencies. * 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled*/ enum { @@ -308,10 +310,30 @@ struct soc_intel_cannonlake_config { * PchSerialIoIndexUART2 * * Mode select: + * For Cannonlake PCH following values are supported: + * PchSerialIoNotInitialized * PchSerialIoDisabled * PchSerialIoPci * PchSerialIoAcpi * PchSerialIoHidden + * PchSerialIoMax + * + * For Cometlake following values are supported: + * PchSerialIoNotInitialized + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit, + * PchSerialIoMax + * + * NOTE: + * PchSerialIoNotInitialized is not an option provided by FSP, this + * option is default selected in case devicetree doesn't fill this param + * In case PchSerialIoNotInitialized is selected or an invalid value is + * provided from devicetree, coreboot will configure device into PCI + * mode by default. + * */ uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 318b8a25ae..e3a2310d5c 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2018-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +25,69 @@ #include <soc/ramstage.h> #include <string.h> +static const int serial_io_dev[] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 +}; + +static uint8_t get_param_value(const config_t *config, uint32_t dev_offset) +{ + struct device *dev; + + dev = dev_find_slot(0, serial_io_dev[dev_offset]); + if (!dev || !dev->enabled) + return PchSerialIoDisabled; + + if ((config->SerialIoDevMode[dev_offset] >= PchSerialIoMax) || + (config->SerialIoDevMode[dev_offset] == PchSerialIoNotInitialized)) + return PchSerialIoPci; + + /* + * Correct Enum index starts from 1, so subtract 1 while returning value + */ + return config->SerialIoDevMode[dev_offset] - 1; +} + +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) +static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params) +{ + uint32_t dev_offset = 0; + uint32_t i = 0; + + for (i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++, dev_offset++) { + params->SerialIoI2cMode[i] = + get_param_value(config, dev_offset); + } + + for (i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++, + dev_offset++) { + params->SerialIoSpiMode[i] = + get_param_value(config, dev_offset); + } + + for (i = 0; i < SOC_INTEL_CML_UART_DEV_MAX; i++, dev_offset++) { + params->SerialIoUartMode[i] = + get_param_value(config, dev_offset); + } +} +#else +static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params) +{ + for (int i = 0; i < ARRAY_SIZE(serial_io_dev); i++) + params->SerialIoDevMode[i] = get_param_value(config, i); +} +#endif + static void parse_devicetree(FSP_S_CONFIG *params) { struct device *dev = SA_DEV_ROOT; @@ -34,32 +97,8 @@ static void parse_devicetree(FSP_S_CONFIG *params) } const config_t *config = dev->chip_info; - const int SerialIoDev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 - }; - - for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) { - dev = dev_find_slot(0, SerialIoDev[i]); - if (!dev->enabled) { - params->SerialIoDevMode[i] = PchSerialIoDisabled; - continue; - } - params->SerialIoDevMode[i] = PchSerialIoPci; - if (config->SerialIoDevMode[i] == PchSerialIoAcpi || - config->SerialIoDevMode[i] == PchSerialIoHidden) - params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; - } + + parse_devicetree_param(config, params); } /* UPD parameters to be initialized before SiliconInit */ @@ -175,8 +214,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable CNVi Wifi if enabled in device tree */ dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) + params->CnviMode = dev->enabled; +#else params->PchCnviMode = dev->enabled; - +#endif /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { if (config->PcieClkSrcUsage[i] == 0) diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h index e152770024..6c95356d4e 100644 --- a/src/soc/intel/cannonlake/include/soc/serialio.h +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,12 +17,26 @@ #ifndef _SERIALIO_H_ #define _SERIALIO_H_ +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) typedef enum { + PchSerialIoNotInitialized, + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoHidden, + PchSerialIoLegacyUart, + PchSerialIoSkipInit, + PchSerialIoMax, +} PCH_SERIAL_IO_MODE; +#else +typedef enum { + PchSerialIoNotInitialized, PchSerialIoDisabled, PchSerialIoPci, PchSerialIoAcpi, PchSerialIoHidden, + PchSerialIoMax, } PCH_SERIAL_IO_MODE; +#endif typedef enum { PchSerialIoIndexI2C0, |