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-rw-r--r--src/superio/nuvoton/Makefile.inc1
-rw-r--r--src/superio/nuvoton/npcd378/Kconfig18
-rw-r--r--src/superio/nuvoton/npcd378/Makefile.inc17
-rw-r--r--src/superio/nuvoton/npcd378/acpi/superio.asl168
-rw-r--r--src/superio/nuvoton/npcd378/npcd378.h37
-rw-r--r--src/superio/nuvoton/npcd378/superio.c87
6 files changed, 328 insertions, 0 deletions
diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc
index b557af2685..0a4b357a20 100644
--- a/src/superio/nuvoton/Makefile.inc
+++ b/src/superio/nuvoton/Makefile.inc
@@ -25,3 +25,4 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d
+subdirs-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += npcd378
diff --git a/src/superio/nuvoton/npcd378/Kconfig b/src/superio/nuvoton/npcd378/Kconfig
new file mode 100644
index 0000000000..d405e29ad7
--- /dev/null
+++ b/src/superio/nuvoton/npcd378/Kconfig
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_NUVOTON_NPCD378
+ bool
+ select SUPERIO_NUVOTON_COMMON_ROMSTAGE
diff --git a/src/superio/nuvoton/npcd378/Makefile.inc b/src/superio/nuvoton/npcd378/Makefile.inc
new file mode 100644
index 0000000000..ca0c824cdd
--- /dev/null
+++ b/src/superio/nuvoton/npcd378/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += superio.c
diff --git a/src/superio/nuvoton/npcd378/acpi/superio.asl b/src/superio/nuvoton/npcd378/acpi/superio.asl
new file mode 100644
index 0000000000..963704e0ae
--- /dev/null
+++ b/src/superio/nuvoton/npcd378/acpi/superio.asl
@@ -0,0 +1,168 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de>
+ * Copyright (C) 2013, 2016 secunet Security Networks AG
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Include this file into a mainboard's DSDT _SB device tree and it will
+ * expose the NPCD378 SuperIO and some of its functionality.
+ *
+ * It allows the change of IO ports, IRQs and DMA settings on logical
+ * devices, disabling and reenabling logical devices.
+ *
+ * LDN State
+ * 0x2 SP1 Implemented, untested
+ * 0x5 KBCK Implemented, untested
+ */
+
+#undef SUPERIO_CHIP_NAME
+#define SUPERIO_CHIP_NAME NPCD378
+#include <superio/acpi/pnp.asl>
+
+#undef PNP_DEFAULT_PSC
+#define PNP_DEFAULT_PSC Return (0) /* no power management */
+
+Device(SUPERIO_DEV) {
+ Name (_HID, EisaId("PNP0A05"))
+ Name (_STR, Unicode("Nuvoton NPCD378 Super I/O"))
+ Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
+
+ /* SuperIO configuration ports */
+ OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
+ Field (CREG, ByteAcc, NoLock, Preserve)
+ {
+ PNP_ADDR_REG, 8,
+ PNP_DATA_REG, 8,
+ }
+ IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
+
+ Offset (0x30),
+ PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
+ ACT1, 1, /* Logical device activation */
+ ACT2, 1, /* Logical device activation */
+ ACT3, 1, /* Logical device activation */
+ ACT4, 1, /* Logical device activation */
+ ACT5, 1, /* Logical device activation */
+ ACT6, 1, /* Logical device activation */
+ ACT7, 1, /* Logical device activation */
+
+ Offset (0x60),
+ PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
+ PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
+ Offset (0x62),
+ PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
+ PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
+ Offset (0x64),
+ PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */
+ PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */
+
+ Offset (0x70),
+ PNP_IRQ0, 8, /* First IRQ */
+ Offset (0x72),
+ PNP_IRQ1, 8, /* Second IRQ */
+ }
+
+ Method (_CRS)
+ {
+ /* Announce the used I/O ports to the OS */
+ Return (ResourceTemplate () {
+ IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
+ })
+ }
+
+ #undef PNP_ENTER_MAGIC_1ST
+ #undef PNP_ENTER_MAGIC_2ND
+ #undef PNP_ENTER_MAGIC_3RD
+ #undef PNP_ENTER_MAGIC_4TH
+ #undef PNP_EXIT_MAGIC_1ST
+ #undef PNP_EXIT_SPECIAL_REG
+ #undef PNP_EXIT_SPECIAL_VAL
+ #define PNP_ENTER_MAGIC_1ST 0x87
+ #define PNP_ENTER_MAGIC_2ND 0x87
+ #define PNP_EXIT_MAGIC_1ST 0xaa
+ #include <superio/acpi/pnp_config.asl>
+
+#ifdef SUPERIO_SHOW_LPT
+ #undef SUPERIO_PNP_HID
+ #undef SUPERIO_PNP_LDN
+ #undef SUPERIO_PNP_DDN
+ #undef SUPERIO_PNP_PM_REG
+ #undef SUPERIO_PNP_PM_VAL
+ #undef SUPERIO_PNP_PM_LDN
+ #undef SUPERIO_PNP_IO0
+ #undef SUPERIO_PNP_IO1
+ #undef SUPERIO_PNP_IRQ0
+ #undef SUPERIO_PNP_IRQ1
+ #undef SUPERIO_PNP_DMA
+ #undef PNP_DEVICE_ACTIVE
+ #define PNP_DEVICE_ACTIVE ACT3
+ #define SUPERIO_PNP_LDN 1
+ #define SUPERIO_PNP_IO0 0x08, 0x08
+ #include <superio/acpi/pnp_generic.asl>
+#endif
+
+#ifdef SUPERIO_SHOW_SP1
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 2
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef SUPERIO_SHOW_SP2
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 3
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef SUPERIO_SHOW_KBC
+ #undef SUPERIO_KBC_LDN
+ #undef SUPERIO_KBC_PS2M
+ #undef SUPERIO_KBC_PS2LDN
+ #define SUPERIO_KBC_PS2LDN 5
+ #define SUPERIO_KBC_LDN 6
+ #include <superio/acpi/pnp_kbc.asl>
+#endif
+
+#ifdef SUPERIO_SHOW_GPIO
+ #undef SUPERIO_PNP_HID
+ #undef SUPERIO_PNP_LDN
+ #undef SUPERIO_PNP_DDN
+ #undef SUPERIO_PNP_PM_REG
+ #undef SUPERIO_PNP_PM_VAL
+ #undef SUPERIO_PNP_PM_LDN
+ #undef SUPERIO_PNP_IO0
+ #undef SUPERIO_PNP_IO1
+ #undef SUPERIO_PNP_IO2
+ #undef SUPERIO_PNP_IRQ0
+ #undef SUPERIO_PNP_IRQ1
+ #undef SUPERIO_PNP_DMA
+ #undef PNP_DEVICE_ACTIVE
+ #define PNP_DEVICE_ACTIVE ACT3
+ #define SUPERIO_PNP_LDN 8
+ #define SUPERIO_PNP_IO0 0x08, 0x08
+ #include <superio/acpi/pnp_generic.asl>
+#endif
+}
diff --git a/src/superio/nuvoton/npcd378/npcd378.h b/src/superio/nuvoton/npcd378/npcd378.h
new file mode 100644
index 0000000000..732dd000f3
--- /dev/null
+++ b/src/superio/nuvoton/npcd378/npcd378.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_NUVOTON_NPCD378_H
+#define SUPERIO_NUVOTON_NPCD378_H
+
+/* Logical Device Numbers (LDN). */
+/* Default Nuvoton hardware: */
+#define NPCD378_FDC 0x00 /* Floppy */
+#define NPCD378_PP 0x01 /* Parallel port */
+#define NPCD378_SP1 0x02 /* Com1 */
+#define NPCD378_SP2 0x03 /* Com2 & IR */
+#define NPCD378_PWR 0x04 /* LED and PWR button control */
+#define NPCD378_AUX 0x05 /* PS/2 mouse */
+#define NPCD378_KBC 0x06 /* PS/2 keyboard */
+/* The following is guessed based on observation and might be wrong: */
+#define NPCD378_WDT1 0x07
+#define NPCD378_HWM 0x08 /* HWM: 16 pages with each 255 byte */
+#define NPCD378_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */
+#define NPCD378_I2C 0x15 /* Provides 35Khz at IOBASE + 0x9 */
+#define NPCD378_SUSPEND 0x1c /* Suspend control ? */
+#define NPCD378_GPIOA 0x1e
+
+#endif /* SUPERIO_NUVOTON_NPCD378_H */
diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c
new file mode 100644
index 0000000000..d468884c82
--- /dev/null
+++ b/src/superio/nuvoton/npcd378/superio.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de>
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include <superio/conf_mode.h>
+
+#include "npcd378.h"
+
+static void npcd378_init(struct device *dev)
+{
+ if (!dev->enabled)
+ return;
+
+ switch (dev->path.pnp.device) {
+ /* TODO: Might potentially need code for HWM or FDC etc. */
+ case NPCD378_KBC:
+ pc_keyboard_init(PROBE_AUX_DEVICE);
+ break;
+ }
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = npcd378_init,
+ .ops_pnp_mode = &pnp_conf_mode_8787_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, NPCD378_FDC, PNP_IO0|PNP_IRQ0|PNP_DRQ0, 0x0ff8, },
+ { &ops, NPCD378_PP, PNP_IO0|PNP_IRQ0|PNP_DRQ0, 0x0ff8, },
+ { &ops, NPCD378_SP1, PNP_IO0|PNP_IRQ0, 0x0ff8, },
+ { &ops, NPCD378_SP2, PNP_IO0|PNP_IRQ0, 0x0ff8, },
+ { &ops, NPCD378_PWR, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_MSC0|
+ PNP_MSC1|PNP_MSC2|PNP_MSC3|PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|
+ PNP_MSC8|PNP_MSC9|PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE,
+ 0x0ff8, 0x0ff8},
+ { &ops, NPCD378_AUX, PNP_IRQ0, 0x0fff, 0x0fff, },
+ { &ops, NPCD378_KBC, PNP_IO0|PNP_IO1|PNP_IRQ0,
+ 0x0fff, 0x0fff, },
+ { &ops, NPCD378_WDT1, PNP_IO0|PNP_MSC8|PNP_MSC9|
+ PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE, 0x0ff8},
+ { &ops, NPCD378_HWM, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|
+ PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_IRQ0, 0x0ff8},
+ { &ops, NPCD378_GPIO_PP_OD, PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|
+ PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_MSC8|PNP_MSC9|PNP_MSCA|
+ PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE},
+ { &ops, NPCD378_I2C, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_MSC0|
+ PNP_MSC1|PNP_MSC2|PNP_MSC3|PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|
+ PNP_MSC8|PNP_MSC9|PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE,
+ 0x0ff8, 0x0ff8},
+ { &ops, NPCD378_SUSPEND, PNP_IO0, 0x0ff8 },
+ { &ops, NPCD378_GPIOA, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|
+ PNP_MSC4, 0x0ff8},
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nuvoton_npcd378_ops = {
+ CHIP_NAME("NUVOTON NPCD378 Super I/O")
+ .enable_dev = enable_dev,
+};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 02:51:53 +0000