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-rw-r--r--src/mainboard/amd/inagua/OemCustomize.c18
-rw-r--r--src/mainboard/amd/inagua/buildOpts.c78
-rw-r--r--src/mainboard/amd/olivehill/OemCustomize.c31
-rw-r--r--src/mainboard/amd/olivehill/buildOpts.c95
-rw-r--r--src/mainboard/amd/parmer/OemCustomize.c23
-rw-r--r--src/mainboard/amd/parmer/buildOpts.c87
-rw-r--r--src/mainboard/amd/persimmon/OemCustomize.c18
-rw-r--r--src/mainboard/amd/persimmon/buildOpts.c78
-rw-r--r--src/mainboard/amd/south_station/OemCustomize.c18
-rw-r--r--src/mainboard/amd/south_station/buildOpts.c78
-rw-r--r--src/mainboard/amd/thatcher/OemCustomize.c23
-rw-r--r--src/mainboard/amd/thatcher/buildOpts.c87
-rw-r--r--src/mainboard/amd/union_station/OemCustomize.c18
-rw-r--r--src/mainboard/amd/union_station/buildOpts.c78
-rw-r--r--src/mainboard/asrock/e350m1/OemCustomize.c18
-rw-r--r--src/mainboard/asrock/e350m1/buildOpts.c78
-rw-r--r--src/mainboard/asrock/imb-a180/OemCustomize.c32
-rw-r--r--src/mainboard/asrock/imb-a180/buildOpts.c95
-rw-r--r--src/mainboard/asus/f2a85-m/OemCustomize.c28
-rw-r--r--src/mainboard/asus/f2a85-m/buildOpts.c84
-rw-r--r--src/mainboard/asus/f2a85-m_le/OemCustomize.c27
-rw-r--r--src/mainboard/asus/f2a85-m_le/buildOpts.c85
-rw-r--r--src/mainboard/bap/ode_e20XX/OemCustomize.c38
-rw-r--r--src/mainboard/bap/ode_e20XX/buildOpts.c102
-rw-r--r--src/mainboard/biostar/am1ml/OemCustomize.c31
-rw-r--r--src/mainboard/biostar/am1ml/buildOpts.c95
-rw-r--r--src/mainboard/gizmosphere/gizmo/OemCustomize.c29
-rw-r--r--src/mainboard/gizmosphere/gizmo/buildOpts.c89
-rw-r--r--src/mainboard/gizmosphere/gizmo2/OemCustomize.c38
-rw-r--r--src/mainboard/gizmosphere/gizmo2/buildOpts.c102
-rw-r--r--src/mainboard/hp/abm/OemCustomize.c31
-rw-r--r--src/mainboard/hp/abm/buildOpts.c95
-rw-r--r--src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c25
-rw-r--r--src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c23
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c16
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/buildOpts.c14
-rw-r--r--src/mainboard/lenovo/g505s/OemCustomize.c25
-rw-r--r--src/mainboard/lenovo/g505s/buildOpts.c23
-rw-r--r--src/mainboard/lippert/frontrunner-af/OemCustomize.c19
-rw-r--r--src/mainboard/lippert/frontrunner-af/buildOpts.c79
-rw-r--r--src/mainboard/lippert/toucan-af/OemCustomize.c19
-rw-r--r--src/mainboard/lippert/toucan-af/buildOpts.c79
-rw-r--r--src/mainboard/pcengines/apu1/OemCustomize.c29
-rw-r--r--src/mainboard/pcengines/apu1/buildOpts.c90
-rw-r--r--src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h1
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h1
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h1
47 files changed, 554 insertions, 1717 deletions
diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c
index c05480f164..d1f715c38d 100644
--- a/src/mainboard/amd/inagua/OemCustomize.c
+++ b/src/mainboard/amd/inagua/OemCustomize.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
+#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
@@ -128,6 +129,23 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 57590a2e75..b4651b6bb3 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -310,81 +310,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data.
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c
index 0e307ee092..70c50352af 100644
--- a/src/mainboard/amd/olivehill/OemCustomize.c
+++ b/src/mainboard/amd/olivehill/OemCustomize.c
@@ -17,6 +17,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
@@ -151,6 +152,36 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ #define SEED_A 0x12
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+ SEED_A),
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ MOTHER_BOARD_LAYERS (LAYERS_4),
+
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c
index 18e403f325..153d8562ca 100644
--- a/src/mainboard/amd/olivehill/buildOpts.c
+++ b/src/mainboard/amd/olivehill/buildOpts.c
@@ -355,98 +355,3 @@ GPIO_CONTROL olivehill_gpio[] = {
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
- #define SEED_A 0x12
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
- SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
- SEED_A),
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- MOTHER_BOARD_LAYERS (LAYERS_4),
-
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
-
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c
index 36759791f8..fb6177a0f0 100644
--- a/src/mainboard/amd/parmer/OemCustomize.c
+++ b/src/mainboard/amd/parmer/OemCustomize.c
@@ -17,6 +17,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
@@ -198,6 +199,28 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 41b3e398e9..e7ee47dedf 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -356,90 +356,3 @@ GPIO_CONTROL parmer_gpio[] = {
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c
index c8a344794c..825364ecbc 100644
--- a/src/mainboard/amd/persimmon/OemCustomize.c
+++ b/src/mainboard/amd/persimmon/OemCustomize.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
+#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
@@ -134,6 +135,23 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index 23e2706a3f..1ded047f68 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -310,81 +310,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data.
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c
index c88d6aed29..74b0aa8e17 100644
--- a/src/mainboard/amd/south_station/OemCustomize.c
+++ b/src/mainboard/amd/south_station/OemCustomize.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
+#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
@@ -136,6 +137,23 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index ad4047a79e..7f07ea1210 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -310,81 +310,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data.
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c
index 75694f1711..66058f2a4c 100644
--- a/src/mainboard/amd/thatcher/OemCustomize.c
+++ b/src/mainboard/amd/thatcher/OemCustomize.c
@@ -17,6 +17,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
@@ -224,6 +225,28 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index 94d842a836..a26f6971b3 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -356,90 +356,3 @@ GPIO_CONTROL thatcher_gpio[] = {
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c
index 335ee93036..6f4dbfc368 100644
--- a/src/mainboard/amd/union_station/OemCustomize.c
+++ b/src/mainboard/amd/union_station/OemCustomize.c
@@ -17,6 +17,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
@@ -142,6 +143,23 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index ad4047a79e..7f07ea1210 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -310,81 +310,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data.
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c
index 4085f3e589..ab563ae1b3 100644
--- a/src/mainboard/asrock/e350m1/OemCustomize.c
+++ b/src/mainboard/asrock/e350m1/OemCustomize.c
@@ -17,6 +17,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
@@ -122,6 +123,23 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index 140ece4338..2fba932d62 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -310,81 +310,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data.
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c
index 63fed83b66..aec1343f02 100644
--- a/src/mainboard/asrock/imb-a180/OemCustomize.c
+++ b/src/mainboard/asrock/imb-a180/OemCustomize.c
@@ -17,6 +17,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
@@ -151,6 +152,37 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ #define SEED_A 0x12
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+ SEED_A),
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ MOTHER_BOARD_LAYERS (LAYERS_4),
+
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c
index 742646cf4c..a21b55d949 100644
--- a/src/mainboard/asrock/imb-a180/buildOpts.c
+++ b/src/mainboard/asrock/imb-a180/buildOpts.c
@@ -355,98 +355,3 @@ GPIO_CONTROL imba180_gpio[] = {
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
- #define SEED_A 0x12
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
- SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
- SEED_A),
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- MOTHER_BOARD_LAYERS (LAYERS_4),
-
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
-
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c
index 469a87b1bc..6348d5a9cb 100644
--- a/src/mainboard/asus/f2a85-m/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m/OemCustomize.c
@@ -19,6 +19,7 @@
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
@@ -199,6 +200,33 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M)
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+/*
+ TODO: is this OK for DDR3 socket FM2?
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ */
+ PSO_END
+};
+#endif /* CONFIG_BOARD_ASUS_F2A85_M */
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index 83f96f9276..17ce5d25b8 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -358,87 +358,3 @@ GPIO_CONTROL f2a85_m_gpio[] = {
/* Moving this include up will break AGESA. */
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
-/*
- TODO: is this OK for DDR3 socket FM2?
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- */
- PSO_END
-};
diff --git a/src/mainboard/asus/f2a85-m_le/OemCustomize.c b/src/mainboard/asus/f2a85-m_le/OemCustomize.c
index c8a48d9319..ea1c8716ee 100644
--- a/src/mainboard/asus/f2a85-m_le/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m_le/OemCustomize.c
@@ -1 +1,28 @@
#include "../f2a85-m/OemCustomize.c"
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+
+/*
+ TODO: is this OK for DDR3 socket FM2?
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ */
+ PSO_END
+};
+#endif /* CONFIG_BOARD_ASUS_F2A85M_LE */
diff --git a/src/mainboard/asus/f2a85-m_le/buildOpts.c b/src/mainboard/asus/f2a85-m_le/buildOpts.c
index c6810f1052..8233482f62 100644
--- a/src/mainboard/asus/f2a85-m_le/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m_le/buildOpts.c
@@ -358,88 +358,3 @@ GPIO_CONTROL f2a85_m_gpio[] = {
/* Moving this include up will break AGESA. */
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
-
-/*
- TODO: is this OK for DDR3 socket FM2?
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- */
- PSO_END
-};
diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c
index ec0c3d3d92..7feab3a4cb 100644
--- a/src/mainboard/bap/ode_e20XX/OemCustomize.c
+++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c
@@ -17,6 +17,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
@@ -145,6 +146,43 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ #define SEED_WL 0x0E
+ WRITE_LEVELING_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
+ SEED_WL),
+
+ #define SEED_A 0x12
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+ SEED_A),
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ MOTHER_BOARD_LAYERS (LAYERS_6),
+
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c
index 8162d428a8..80cb79f62b 100644
--- a/src/mainboard/bap/ode_e20XX/buildOpts.c
+++ b/src/mainboard/bap/ode_e20XX/buildOpts.c
@@ -357,105 +357,3 @@ GPIO_CONTROL gizmo2_gpio[] = {
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
-
- #define SEED_WL 0x0E
- WRITE_LEVELING_SEED(
- ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
- SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
- SEED_WL),
-
- #define SEED_A 0x12
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
- SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
- SEED_A),
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- MOTHER_BOARD_LAYERS (LAYERS_6),
-
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
-
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c
index 63fed83b66..c44a9944c2 100644
--- a/src/mainboard/biostar/am1ml/OemCustomize.c
+++ b/src/mainboard/biostar/am1ml/OemCustomize.c
@@ -17,6 +17,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
@@ -151,6 +152,36 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ #define SEED_A 0x12
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+ SEED_A),
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ MOTHER_BOARD_LAYERS (LAYERS_4),
+
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c
index 075fe5702f..4f910dfc05 100644
--- a/src/mainboard/biostar/am1ml/buildOpts.c
+++ b/src/mainboard/biostar/am1ml/buildOpts.c
@@ -355,98 +355,3 @@ GPIO_CONTROL imba180_gpio[] = {
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
- #define SEED_A 0x12
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
- SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
- SEED_A),
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- MOTHER_BOARD_LAYERS (LAYERS_4),
-
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
-
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c
index c85430ddb4..2184fb2c88 100644
--- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c
+++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c
@@ -18,6 +18,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
@@ -139,6 +140,34 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
+
+ // Gizmos soldered down memory uses memory CLK0 and CLK1 on CS0
+ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+
+ // Gizmos soldered down memory requires different seeds
+#define WLSEED 0x08
+#define RXSEED 0x40
+ WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
+ HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
index 827980280b..c838baba9a 100644
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c
@@ -312,92 +312,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data.
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
-
- // Gizmos soldered down memory uses memory CLK0 and CLK1 on CS0
- MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-
- // Gizmos soldered down memory requires different seeds
-#define WLSEED 0x08
-#define RXSEED 0x40
- WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
- HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
-
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
index 1d71f897f2..933b036a45 100644
--- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
+++ b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
@@ -17,6 +17,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
@@ -145,6 +146,43 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ #define SEED_WL 0x0E
+ WRITE_LEVELING_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
+ SEED_WL),
+
+ #define SEED_A 0x12
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+ SEED_A),
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ MOTHER_BOARD_LAYERS (LAYERS_6),
+
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c
index 8162d428a8..80cb79f62b 100644
--- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c
@@ -357,105 +357,3 @@ GPIO_CONTROL gizmo2_gpio[] = {
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
-
- #define SEED_WL 0x0E
- WRITE_LEVELING_SEED(
- ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
- SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
- SEED_WL),
-
- #define SEED_A 0x12
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
- SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
- SEED_A),
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- MOTHER_BOARD_LAYERS (LAYERS_6),
-
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
-
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c
index 29eca1deeb..730c97e26e 100644
--- a/src/mainboard/hp/abm/OemCustomize.c
+++ b/src/mainboard/hp/abm/OemCustomize.c
@@ -18,6 +18,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
@@ -147,6 +148,36 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ #define SEED_A 0x12
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+ SEED_A),
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, ONE_DIMM),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
+ MOTHER_BOARD_LAYERS (LAYERS_6),
+
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c
index 96d59db3d1..c24dd4d524 100644
--- a/src/mainboard/hp/abm/buildOpts.c
+++ b/src/mainboard/hp/abm/buildOpts.c
@@ -369,98 +369,3 @@ GPIO_CONTROL hp_abm_gpio[] = {
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Speicifes the HW RXEN training seed for a channel of a socket
- //
- #define SEED_A 0x12
- HW_RXEN_SEED(
- ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
- SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
- SEED_A),
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, ONE_DIMM),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
- MOTHER_BOARD_LAYERS (LAYERS_6),
-
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
-
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
index 9ea6c656c9..605c7d3f9c 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
@@ -19,6 +19,7 @@
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
@@ -197,6 +198,30 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform
+ * information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...).
+ * If PlatformSpecificTable is populated, AGESA will base its settings on the
+ * data from the table. Otherwise, it will use its default conservative settings
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index 8d02f03311..f4b61ab502 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -402,26 +402,3 @@ SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
/* AGESA nonsense: this header depends on the definitions above */
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform
- * information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...).
- * If PlatformSpecificTable is populated, AGESA will base its settings on the
- * data from the table. Otherwise, it will use its default conservative settings
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-
- PSO_END
-};
diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
index a4c6f95a4a..f980a15b08 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
@@ -19,6 +19,7 @@
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
+#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
@@ -178,6 +179,21 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
return AGESA_SUCCESS;
}
+/**
+ * @brief Customer Overides Memory Table
+ *
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform
+ * information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...).
+ * If PlatformSpecificTable is populated, AGESA will base its settings on the
+ * data from the table. Otherwise, it will use its default conservative settings.
+ */
+const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index 73673ef62f..05ea68133b 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -315,17 +315,3 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
/* Instantiate all solution relevant data. */
#include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h>
-/**
- * @brief Customer Overides Memory Table
- *
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform
- * information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...).
- * If PlatformSpecificTable is populated, AGESA will base its settings on the
- * data from the table. Otherwise, it will use its default conservative settings.
- */
-const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- PSO_END
-};
diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c
index 9ea6c656c9..605c7d3f9c 100644
--- a/src/mainboard/lenovo/g505s/OemCustomize.c
+++ b/src/mainboard/lenovo/g505s/OemCustomize.c
@@ -19,6 +19,7 @@
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
@@ -197,6 +198,30 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform
+ * information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...).
+ * If PlatformSpecificTable is populated, AGESA will base its settings on the
+ * data from the table. Otherwise, it will use its default conservative settings
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index 7b491d41fc..d633d07897 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -402,26 +402,3 @@ SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {
/* AGESA nonsense: this header depends on the definitions above */
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform
- * information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...).
- * If PlatformSpecificTable is populated, AGESA will base its settings on the
- * data from the table. Otherwise, it will use its default conservative settings
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-
- PSO_END
-};
diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/OemCustomize.c
index 0332580ae7..63466b9dfb 100644
--- a/src/mainboard/lippert/frontrunner-af/OemCustomize.c
+++ b/src/mainboard/lippert/frontrunner-af/OemCustomize.c
@@ -17,6 +17,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
@@ -140,6 +141,24 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
index 3211966586..c17394a8bb 100644
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c
@@ -311,82 +311,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data.
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/toucan-af/OemCustomize.c
index 93e59a48f4..a5f4921de2 100644
--- a/src/mainboard/lippert/toucan-af/OemCustomize.c
+++ b/src/mainboard/lippert/toucan-af/OemCustomize.c
@@ -17,6 +17,7 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
+#include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
@@ -140,6 +141,24 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c
index 3211966586..c17394a8bb 100644
--- a/src/mainboard/lippert/toucan-af/buildOpts.c
+++ b/src/mainboard/lippert/toucan-af/buildOpts.c
@@ -311,82 +311,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data.
#include "PlatformInstall.h"
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
- HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c
index d3dd403cb5..20acb272ac 100644
--- a/src/mainboard/pcengines/apu1/OemCustomize.c
+++ b/src/mainboard/pcengines/apu1/OemCustomize.c
@@ -19,6 +19,7 @@
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
+#include <PlatformMemoryConfiguration.h>
/**
* OemCustomizeInitEarly
@@ -126,6 +127,34 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
return AGESA_SUCCESS;
}
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
+
+ // APU soldered down memory uses memory CLK0 and CLK1 on CS0
+ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+
+ // APU soldered down memory requires different seeds
+#define WLSEED 0x08
+#define RXSEED 0x40
+ WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
+ HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
+
+ PSO_END
+};
+
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
index 50cf4cfa86..edfdd301a1 100644
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ b/src/mainboard/pcengines/apu1/buildOpts.c
@@ -309,93 +309,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data.
#include "PlatformInstall.h"
-
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
- //
- // The following macros are supported (use comma to separate macros):
- //
- // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
- // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
- // AGESA will base on this value to disable unused MemClk to save power.
- // Example:
- // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
- // Bit AM3/S1g3 pin name
- // 0 M[B,A]_CLK_H/L[0]
- // 1 M[B,A]_CLK_H/L[1]
- // 2 M[B,A]_CLK_H/L[2]
- // 3 M[B,A]_CLK_H/L[3]
- // 4 M[B,A]_CLK_H/L[4]
- // 5 M[B,A]_CLK_H/L[5]
- // 6 M[B,A]_CLK_H/L[6]
- // 7 M[B,A]_CLK_H/L[7]
- // And platform has the following routing:
- // CS0 M[B,A]_CLK_H/L[4]
- // CS1 M[B,A]_CLK_H/L[2]
- // CS2 M[B,A]_CLK_H/L[3]
- // CS3 M[B,A]_CLK_H/L[5]
- // Then platform can specify the following macro:
- // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
- //
- // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
- // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
- // AGESA will base on this value to tristate unused CKE to save power.
- //
- // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
- // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
- // AGESA will base on this value to tristate unused ODT pins to save power.
- //
- // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
- // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
- // AGESA will base on this value to tristate unused Chip select to save power.
- //
- // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
- // Specifies the number of DIMM slots per channel.
- //
- // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
- // Specifies the number of Chip selects per channel.
- //
- // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
- // Specifies the number of channels per socket.
- //
- // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
- // Specifies DDR bus speed of channel ChannelID on socket SocketID.
- //
- // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
- // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
- //
- // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
- // Byte6Seed, Byte7Seed, ByteEccSeed)
- // Specifies the write leveling seed for a channel of a socket.
- //
-
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
-
- // APU soldered down memory uses memory CLK0 and CLK1 on CS0
- MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-
- // APU soldered down memory requires different seeds
-#define WLSEED 0x08
-#define RXSEED 0x40
- WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
- HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
-
- PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"
diff --git a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h
index 8641589f96..085abc6282 100644
--- a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h
@@ -2160,7 +2160,6 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#include "OptionsHt.h"
#include "OptionHtInstall.h"
#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
#include "OptionMemoryInstall.h"
#include "OptionMemoryRecovery.h"
#include "OptionMemoryRecoveryInstall.h"
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h
index eca567b3ff..cbf7ac6ade 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h
@@ -2623,7 +2623,6 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#include "OptionsHt.h"
#include "OptionHtInstall.h"
#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
#include "OptionMemoryInstall.h"
#include "OptionMemoryRecovery.h"
#include "OptionMemoryRecoveryInstall.h"
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
index 1295888f99..e989537df6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
@@ -1732,7 +1732,6 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#include "OptionsHt.h"
#include "OptionHtInstall.h"
#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
#include "OptionMemoryInstall.h"
#include "OptionMemoryRecovery.h"
#include "OptionMemoryRecoveryInstall.h"