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-rw-r--r--src/arch/x86/include/arch/cpu.h6
-rw-r--r--src/arch/x86/postcar_loader.c12
-rw-r--r--src/cpu/intel/car/romstage.c2
-rw-r--r--src/drivers/intel/fsp1_1/car.c7
-rw-r--r--src/northbridge/intel/e7505/memmap.c2
-rw-r--r--src/northbridge/intel/gm45/memmap.c7
-rw-r--r--src/northbridge/intel/haswell/memmap.c6
-rw-r--r--src/northbridge/intel/i440bx/memmap.c7
-rw-r--r--src/northbridge/intel/i945/memmap.c7
-rw-r--r--src/northbridge/intel/nehalem/memmap.c7
-rw-r--r--src/northbridge/intel/pineview/memmap.c7
-rw-r--r--src/northbridge/intel/sandybridge/memmap.c7
-rw-r--r--src/northbridge/intel/x4x/memmap.c7
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c8
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c6
15 files changed, 24 insertions, 74 deletions
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 606202197e..9aa446ec0a 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -302,6 +302,7 @@ struct postcar_frame {
uint32_t upper_mask;
int max_var_mtrrs;
int num_var_mtrrs;
+ int skip_common_mtrr;
};
/*
@@ -323,6 +324,11 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf,
void postcar_frame_add_romcache(struct postcar_frame *pcf, int type);
/*
+ * Add a common MTRR setup most platforms will have as a subset.
+ */
+void postcar_frame_common_mtrrs(struct postcar_frame *pcf);
+
+/*
* Push used MTRR and Max MTRRs on to the stack
* and return pointer to stack top.
*/
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index 35e139fe1c..b1b2da0540 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -120,6 +120,18 @@ void postcar_frame_add_romcache(struct postcar_frame *pcf, int type)
postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type);
}
+void postcar_frame_common_mtrrs(struct postcar_frame *pcf)
+{
+ if (pcf->skip_common_mtrr)
+ return;
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
+}
+
void *postcar_commit_mtrrs(struct postcar_frame *pcf)
{
/*
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index f6b62192f1..624f3ff9b7 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -33,6 +33,8 @@ static void prepare_and_run_postcar(struct postcar_frame *pcf)
fill_postcar_frame(pcf);
+ postcar_frame_common_mtrrs(pcf);
+
run_postcar_phase(pcf);
/* We do not return here. */
}
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index f6e42d7bfa..b206e6d9c3 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -28,13 +28,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
- MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations. */
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index c3b59e9415..7033f89a04 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -54,6 +54,8 @@ void fill_postcar_frame(struct postcar_frame *pcf)
* operations when source is left as UC.
*/
+ pcf->skip_common_mtrr = 1;
+
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 9337470e1e..71037aedd0 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -138,13 +138,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index 13881e99b2..f43bd2f3bc 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -57,12 +57,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index 084679ff4a..e4e5de7fc3 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -72,13 +72,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache CBMEM region as WB. */
top_of_ram = (uintptr_t)cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 5f3e2569fb..6092c25770 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -104,13 +104,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c
index 1a3a6d7cdf..031240c2f3 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/nehalem/memmap.c
@@ -62,13 +62,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 66900af2ef..2e028892e3 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -154,13 +154,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 99f11a0f2a..83a67abeb8 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -61,13 +61,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
top_of_ram = (uintptr_t)cbmem_top();
/* Cache 8MiB below the top of ram. On sandybridge systems the top of
* ram under 4GiB is the start of the TSEG region. It is required to
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 254ca880fa..a61d64e61d 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -149,13 +149,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index acdf2613fa..8361bb1972 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -62,6 +62,8 @@ static void prepare_and_run_postcar(struct postcar_frame *pcf)
fill_postcar_frame(pcf);
+ postcar_frame_common_mtrrs(pcf);
+
run_postcar_phase(pcf);
/* We do not return here. */
}
@@ -256,12 +258,6 @@ static void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index ca478f7313..5ae39dd767 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -39,12 +39,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 20:50:40 +0000