7 files changed, 35 insertions, 9 deletions
diff --git a/src/Kconfig b/src/Kconfig
index 35acad494e..7f13b62359 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -376,17 +376,9 @@ menu "Mainboard"
 
 source "src/mainboard/Kconfig"
 
+# defaults for CBFS_SIZE are set at the end of the file.
 config CBFS_SIZE
 	hex "Size of CBFS filesystem in ROM"
-	default 0x100000 if HAVE_INTEL_FIRMWARE || \
-	  NORTHBRIDGE_INTEL_X4X || \
-	  NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || \
-	  NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || \
-	  NORTHBRIDGE_INTEL_SANDYBRIDGE || \
-	  NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \
-	  SOC_INTEL_BROADWELL
-	default 0x200000 if SOC_INTEL_SKYLAKE
-	default ROM_SIZE
 	help
 	  This is the part of the ROM actually managed by CBFS, located at the
 	  end of the ROM (passed through cbfstool -o) on x86 and at at the start
@@ -1157,3 +1149,11 @@ config MAX_REBOOT_CNT
 	  Internal option that sets the maximum number of bootblock executions allowed
 	  with the normal image enabled before assuming the normal image is defective
 	  and switching to the fallback image.
+
+config CBFS_SIZE
+	hex
+	default ROM_SIZE
+	help
+	  This is the part of the ROM actually managed by CBFS.  Set it to be
+	  equal to the full rom size if that hasn't been overridden by the
+	  chipset or mainboard.
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 98ce6444e9..6ee65580b0 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -27,6 +27,10 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select INTEL_EDID
 	select INTEL_GMA_ACPI
 
+config CBFS_SIZE
+	hex
+	default 0x100000
+
 config BOOTBLOCK_NORTHBRIDGE_INIT
 	string
 	default "northbridge/intel/gm45/bootblock.c"
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 028921c493..3658bd8ec5 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -25,6 +25,10 @@ config NORTHBRIDGE_INTEL_NEHALEM
 
 if NORTHBRIDGE_INTEL_NEHALEM
 
+config CBFS_SIZE
+	hex
+	default 0x100000
+
 config VGA_BIOS_ID
 	string
 	default "8086,0046"
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 347e3fa966..9d4d089dd1 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -45,6 +45,10 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
 
 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE
 
+config CBFS_SIZE
+	hex
+	default 0x100000
+
 config VGA_BIOS_ID
 	string
 	default "8086,0106"
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index f643bb2a8d..4ee90a4523 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -28,6 +28,10 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select INTEL_GMA_ACPI
 	select EARLY_CBMEM_INIT
 
+config CBFS_SIZE
+	hex
+	default 0x100000
+
 config BOOTBLOCK_NORTHBRIDGE_INIT
 	string
 	default "northbridge/intel/x4x/bootblock.c"
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 0ebdaa4261..c0ce9ad022 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -64,6 +64,10 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "soc/intel/skylake/bootblock/pch.c"
 
+config CBFS_SIZE
+	hex
+	default 0x200000
+
 config CPU_ADDR_BITS
 	int
 	default 36
diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig
index 62b9a31690..c36b235cad 100644
--- a/src/southbridge/intel/common/firmware/Kconfig
+++ b/src/southbridge/intel/common/firmware/Kconfig
@@ -146,4 +146,10 @@ config LOCK_MANAGEMENT_ENGINE
 
 	  If unsure, say N.
 
+config CBFS_SIZE
+	hex
+	default 0x100000
+	help
+	  Reduce CBFS size to give room to the IFD blobs.
+
 endif #INTEL_FIRMWARE