3 files changed, 11 insertions, 11 deletions

diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index c1a3d17475..990d3de388 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -29,7 +29,7 @@
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-	device_t dev;
+	struct device *dev;
 	u32 pciexbar = 0;
 	u32 pciexbar_reg;
 	int max_buses;
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 5ca06a9098..6c3d6ae5f3 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -746,7 +746,7 @@ static void gma_func1_init(struct device *dev)
 		pci_write_config8(dev, 0xf4, 0xff);
 }
 
-static void gma_set_subsystem(device_t dev, unsigned int vendor,
+static void gma_set_subsystem(struct device *dev, unsigned int vendor,
 			unsigned int device)
 {
 	if (!vendor || !device) {
@@ -761,7 +761,7 @@ static void gma_set_subsystem(device_t dev, unsigned int vendor,
 const struct i915_gpu_controller_info *
 intel_gma_get_controller_info(void)
 {
-	device_t dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
+	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
 	if (!dev)
 		return NULL;
 	struct northbridge_intel_i945_config *chip = dev->chip_info;
@@ -770,7 +770,7 @@ intel_gma_get_controller_info(void)
 	return &chip->gfx;
 }
 
-static void gma_ssdt(device_t device)
+static void gma_ssdt(struct device *device)
 {
 	const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
 	if (!gfx)
@@ -779,7 +779,7 @@ static void gma_ssdt(device_t device)
 	drivers_intel_gma_displays_ssdt_generate(gfx);
 }
 
-static void gma_func0_read_resources(device_t dev)
+static void gma_func0_read_resources(struct device *dev)
 {
 	u8 reg8;
 
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index fdb37b1d47..794c61e20e 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -28,7 +28,7 @@
 
 static int get_pcie_bar(u32 *base)
 {
-	device_t dev;
+	struct device *dev;
 	u32 pciexbar_reg;
 
 	*base = 0;
@@ -57,7 +57,7 @@ static int get_pcie_bar(u32 *base)
 	return 0;
 }
 
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
 {
 	uint32_t pci_tolm;
 	uint8_t tolud, reg8;
@@ -149,7 +149,7 @@ static struct device_operations pci_domain_ops = {
 	.ops_pci_bus	  = pci_bus_default_ops,
 };
 
-static void mc_read_resources(device_t dev)
+static void mc_read_resources(struct device *dev)
 {
 	u32 pcie_config_base;
 	int buses;
@@ -163,7 +163,7 @@ static void mc_read_resources(device_t dev)
 	}
 }
 
-static void intel_set_subsystem(device_t dev, unsigned int vendor,
+static void intel_set_subsystem(struct device *dev, unsigned int vendor,
 				unsigned int device)
 {
 	if (!vendor || !device) {
@@ -199,7 +199,7 @@ static const struct pci_driver mc_driver __pci_driver = {
 	.devices = pci_device_ids,
 };
 
-static void cpu_bus_init(device_t dev)
+static void cpu_bus_init(struct device *dev)
 {
 	initialize_cpus(dev->link_list);
 }
@@ -212,7 +212,7 @@ static struct device_operations cpu_bus_ops = {
 	.scan_bus         = 0,
 };
 
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
 {
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_DOMAIN)