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-rw-r--r--src/cpu/amd/model_fxx/init_cpus.c2
-rw-r--r--src/include/cpu/amd/model_fxx_rev.h9
2 files changed, 7 insertions, 4 deletions
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 63c88232bf..d38c552b91 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -342,7 +342,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
static u32 is_core0_started(u32 nodeid)
{
u32 htic;
- device_t device;
+ pci_devfn_t device;
device = PCI_DEV(0, 0x18 + nodeid, 0);
htic = pci_read_config32(device, HT_INIT_CONTROL);
htic &= HTIC_INIT_Detect;
diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h
index be961f21da..4a217b2668 100644
--- a/src/include/cpu/amd/model_fxx_rev.h
+++ b/src/include/cpu/amd/model_fxx_rev.h
@@ -76,8 +76,9 @@ static inline int is_e0_later_in_bsp(int nodeid)
if (nodeid == 0) { // we don't need to do that for node 0 in core0/node0
return !is_cpu_pre_e0();
}
+
// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x18+nodeid,2);
val_old = pci_read_config32(dev, 0x80);
val = val_old;
@@ -85,6 +86,7 @@ static inline int is_e0_later_in_bsp(int nodeid)
pci_write_config32(dev, 0x80, val);
val = pci_read_config32(dev, 0x80);
e0_later = !!(val & (1<<3));
+
if (e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
pci_write_config32(dev, 0x80, val_old); // restore it
}
@@ -95,7 +97,7 @@ static inline int is_e0_later_in_bsp(int nodeid)
static inline int is_cpu_f0_in_bsp(int nodeid)
{
uint32_t dword;
- device_t dev;
+ pci_devfn_t dev;
if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
return 0;
dev = PCI_DEV(0, 0x18+nodeid, 3);
@@ -106,7 +108,8 @@ static inline int is_cpu_f0_in_bsp(int nodeid)
static inline int is_cpu_pre_f2_in_bsp(int nodeid)
{
uint32_t dword;
- device_t dev;
+ pci_devfn_t dev;
+
if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
return 1;
dev = PCI_DEV(0, 0x18+nodeid, 3);