diff options
| -rw-r--r-- | src/mainboard/ocp/wedge100s/romstage.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c index cf52c01f04..1d770366ba 100644 --- a/src/mainboard/ocp/wedge100s/romstage.c +++ b/src/mainboard/ocp/wedge100s/romstage.c @@ -17,6 +17,9 @@ #include <stddef.h> #include <soc/romstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <cpu/x86/msr.h> +#include <cf9_reset.h> +#include <console/console.h> /** * /brief mainboard call for setup that needs to be done before fsp init @@ -24,7 +27,22 @@ */ void early_mainboard_romstage_entry(void) { - + /* + * Sometimes the system boots in an invalid state, where random values + * have been written to MSRs and then the MSRs are locked. + * Seems to always happen on warm reset. + * + * Power cycling or a board_reset() isn't sufficient in this case, so + * issue a full_reset() to "fix" this issue. + * + * It seems to be a deficiency in the reset logic, as other + * FSP broadwell DE boards are not affected. + */ + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + if (msr.lo & 1) { + printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); + full_reset(); + } } /** |