diff options
| -rw-r--r-- | src/cpu/amd/agesa/family14/model_14_init.c | 6 | ||||
| -rw-r--r-- | src/cpu/amd/agesa/family15tn/model_15_init.c | 6 | ||||
| -rw-r--r-- | src/cpu/amd/agesa/family16kb/model_16_init.c | 6 | ||||
| -rw-r--r-- | src/cpu/amd/agesa/s3_resume.h | 7 |
4 files changed, 5 insertions, 20 deletions
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 1a97f2c462..60a88c734e 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -32,9 +32,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam14.h> #include <arch/acpi.h> -#if CONFIG_HAVE_ACPI_RESUME #include <cpu/amd/agesa/s3_resume.h> -#endif #define MCI_STATUS 0x401 @@ -75,10 +73,8 @@ static void model_14_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type == 3) + if (acpi_is_wakeup()) restore_mtrr(); -#endif x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 467a3012df..64c78af04e 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -33,9 +33,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -#if CONFIG_HAVE_ACPI_RESUME #include <cpu/amd/agesa/s3_resume.h> -#endif static void model_15_init(device_t dev) { @@ -73,10 +71,8 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type == 3) + if (acpi_is_wakeup()) restore_mtrr(); -#endif x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 734d9ef7ef..ef31f96c92 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -32,9 +32,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam16.h> #include <arch/acpi.h> -#if CONFIG_HAVE_ACPI_RESUME #include <cpu/amd/agesa/s3_resume.h> -#endif static void model_16_init(device_t dev) { @@ -71,10 +69,8 @@ static void model_16_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type == 3) + if (acpi_is_wakeup()) restore_mtrr(); -#endif x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 6e719c98a7..ebcd690282 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -20,8 +20,6 @@ #ifndef S3_RESUME_H #define S3_RESUME_H -#if CONFIG_HAVE_ACPI_RESUME - /* The size needs to be 4k aligned, which is the sector size of most flashes. */ #define S3_DATA_VOLATILE_SIZE 0x6000 #define S3_DATA_MTRR_SIZE 0x1000 @@ -30,7 +28,8 @@ #define S3_DATA_MTRR_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE) #define S3_DATA_NONVOLATILE_POS (CONFIG_S3_DATA_POS + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE) -#if (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ + (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE #error "Please increase the value of S3_DATA_SIZE" #endif @@ -55,5 +54,3 @@ void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx); #endif #endif - -#endif |