diff options
| -rw-r--r-- | src/mainboard/asus/dsbf/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/supermicro/x7db8/romstage.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/i5000/Kconfig | 10 | ||||
| -rw-r--r-- | src/northbridge/intel/i5000/bootblock.c | 21 |
4 files changed, 30 insertions, 9 deletions
diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index cb63f45d2b..f4e65cbae2 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -129,10 +129,6 @@ void main(unsigned long bist) enable_smbus(); - /* setup PCIe MMCONF base address */ - pci_write_config32(PCI_DEV(0, 16, 0), 0x64, - CONFIG_MMCONF_BASE_ADDRESS >> 16); - smbus_write_byte(0x6f, 0x00, 0x63); smbus_write_byte(0x6f, 0x01, 0x04); smbus_write_byte(0x6f, 0x02, 0x53); diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index fa7341231f..bc54ed7306 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -128,10 +128,6 @@ void main(unsigned long bist) enable_smbus(); - /* setup PCIe MMCONF base address */ - pci_write_config32(PCI_DEV(0, 16, 0), 0x64, - CONFIG_MMCONF_BASE_ADDRESS >> 16); - outb(0x07, 0x11b8); /* These are smbus write captured with serialice. They diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig index b9c3547770..f7344ca97d 100644 --- a/src/northbridge/intel/i5000/Kconfig +++ b/src/northbridge/intel/i5000/Kconfig @@ -20,9 +20,17 @@ config NORTHBRIDGE_INTEL_I5000 bool select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP +if NORTHBRIDGE_INTEL_I5000 + config NORTHBRIDGE_INTEL_I5000_RAM_CHECK bool prompt "Run ramcheck after RAM initialization" - depends on NORTHBRIDGE_INTEL_I5000 + +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/i5000/bootblock.c" + +endif diff --git a/src/northbridge/intel/i5000/bootblock.c b/src/northbridge/intel/i5000/bootblock.c new file mode 100644 index 0000000000..eabbee6d63 --- /dev/null +++ b/src/northbridge/intel/i5000/bootblock.c @@ -0,0 +1,21 @@ +#include <arch/io.h> + +static void bootblock_northbridge_init(void) +{ + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + + /* setup PCIe MMCONF base address */ + pci_io_write_config32(PCI_DEV(0, 16, 0), 0x64, + CONFIG_MMCONF_BASE_ADDRESS >> 16); +} |