diff options
| -rw-r--r-- | src/arch/riscv/Makefile.inc | 12 | ||||
| -rw-r--r-- | src/arch/riscv/bootblock.S | 3 | ||||
| -rw-r--r-- | src/arch/riscv/include/arch/smp/spinlock.h | 2 | ||||
| -rw-r--r-- | src/arch/riscv/include/bits.h | 17 | ||||
| -rw-r--r-- | src/arch/riscv/include/mcall.h | 11 | ||||
| -rw-r--r-- | src/arch/riscv/ramstage.S | 3 | ||||
| -rw-r--r-- | src/arch/riscv/smp.c | 14 | ||||
| -rw-r--r-- | src/lib/libgcc.c | 3 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/Kconfig | 15 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-riscv/Kconfig.name | 7 | ||||
| -rw-r--r-- | src/mainboard/emulation/spike-riscv/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/ucb/riscv/Kconfig | 21 |
12 files changed, 89 insertions, 20 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 9d91f0cefe..d5f62954eb 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -86,6 +86,10 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs) bootblock-c-ccopts += $(riscv_flags) bootblock-S-ccopts += $(riscv_asm_flags) +ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_bootblock += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_BOOTBLOCK_RISCV ################################################################################ @@ -116,6 +120,10 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) +ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_romstage += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_ROMSTAGE_RISCV ################################################################################ @@ -161,5 +169,9 @@ $(objcbfs)/ramstage.debug: $$(ramstage-objs) ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) +ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +LDFLAGS_ramstage += -m elf32lriscv +endif #CONFIG_ARCH_RISCV_RV32 + endif #CONFIG_ARCH_RAMSTAGE_RISCV endif #CONFIG_ARCH_RISCV diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index d4b8be7c2a..b0796f9fbc 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -16,6 +16,7 @@ */ #include <arch/encoding.h> +#include <bits.h> #include <mcall.h> .section ".text._start", "ax", %progbits @@ -44,7 +45,7 @@ _start: slli t1, a0, RISCV_PGSHIFT add t0, t0, t1 li t1, 0xDEADBEEF - sd t1, 0(t0) + STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1 diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h index dc561d30a1..95e60bfefc 100644 --- a/src/arch/riscv/include/arch/smp/spinlock.h +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -21,7 +21,7 @@ #define barrier() { asm volatile ("fence" ::: "memory"); } typedef struct { - volatile atomic_t lock; + atomic_t lock; } spinlock_t; static inline void spinlock_lock(spinlock_t *lock) diff --git a/src/arch/riscv/include/bits.h b/src/arch/riscv/include/bits.h index f69c7ec0da..d824f3ec98 100644 --- a/src/arch/riscv/include/bits.h +++ b/src/arch/riscv/include/bits.h @@ -47,10 +47,19 @@ #define STR(x) XSTR(x) #define XSTR(x) #x -# define SLL32 sllw -# define STORE sd -# define LOAD ld -# define LOG_REGBYTES 3 +#if __riscv_xlen == 64 +#define SLL32 sllw +#define STORE sd +#define LOAD ld +#define LWU lwu +#define LOG_REGBYTES 3 +#else +#define SLL32 sll +#define STORE sw +#define LOAD lw +#define LWU lw +#define LOG_REGBYTES 2 +#endif #define REGBYTES (1 << LOG_REGBYTES) diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index cd1ed6dc18..192d2b4564 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -18,7 +18,13 @@ // NOTE: this is the size of hls_t below. A static_assert would be // nice to have. +#if __riscv_xlen == 64 #define HLS_SIZE 88 +#endif + +#if __riscv_xlen == 32 +#define HLS_SIZE 52 +#endif /* We save 37 registers, currently. */ #define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8) @@ -26,6 +32,7 @@ #ifndef __ASSEMBLER__ #include <arch/encoding.h> +#include <arch/smp/atomic.h> #include <stdint.h> typedef struct { @@ -38,8 +45,8 @@ typedef struct { struct blocker { void *arg; void (*fn)(void *arg); - uint32_t sync_a; - uint32_t sync_b; + atomic_t sync_a; + atomic_t sync_b; }; typedef struct { diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 115a55f290..28183e50e0 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -14,6 +14,7 @@ */ #include <arch/encoding.h> +#include <bits.h> #include <mcall.h> .section ".text._start", "ax", %progbits @@ -27,7 +28,7 @@ _start: slli t1, a0, RISCV_PGSHIFT add t0, t0, t1 li t1, 0xDEADBEEF - sd t1, 0(t0) + STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1 diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index 8942ec5b93..b32e4b8694 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -32,13 +32,13 @@ void smp_pause(int working_hartid) /* waiting for work hart */ do { barrier(); - } while (SYNCA != 0x01234567); + } while (atomic_read(&SYNCA) != 0x01234567); clear_csr(mstatus, MSTATUS_MIE); write_csr(mie, MIP_MSIP); /* count how many cores enter the halt */ - __sync_fetch_and_add(&SYNCB, 1); + atomic_add(&SYNCB, 1); do { barrier(); @@ -49,17 +49,17 @@ void smp_pause(int working_hartid) } else { /* Initialize the counter and * mark the work hart into smp_pause */ - SYNCB = 0; - SYNCA = 0x01234567; + atomic_set(&SYNCB, 0); + atomic_set(&SYNCA, 0x01234567); /* waiting for other Hart to enter the halt */ do { barrier(); - } while (SYNCB + 1 < CONFIG_MAX_CPUS); + } while (atomic_read(&SYNCB) + 1 < CONFIG_MAX_CPUS); /* initialize for the next call */ - SYNCA = 0; - SYNCB = 0; + atomic_set(&SYNCA, 0); + atomic_set(&SYNCB, 0); } #undef SYNCA #undef SYNCB diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c index 99a0749a45..88b3f9be01 100644 --- a/src/lib/libgcc.c +++ b/src/lib/libgcc.c @@ -20,7 +20,8 @@ * <lib.h> in case GCC does not have an assembly version for this arch. */ -#if !IS_ENABLED(CONFIG_ARCH_X86) /* work around lack of --gc-sections on x86 */ +#if !IS_ENABLED(CONFIG_ARCH_X86) /* work around lack of --gc-sections on x86 */ \ + && !IS_ENABLED(CONFIG_ARCH_RISCV_RV32) /* defined in rv32 libgcc.a */ int __clzsi2(u32 a); int __clzsi2(u32 a) { diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index ecaa76468b..d15c99e966 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -16,6 +16,21 @@ # util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf # qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf + +if BOARD_EMULATION_QEMU_RISCV_RV64 + +config BOARD_EMULATION_QEMU_RISCV + def_bool y + select ARCH_RISCV_RV64 +endif + +if BOARD_EMULATION_QEMU_RISCV_RV32 + +config BOARD_EMULATION_QEMU_RISCV + def_bool y + select ARCH_RISCV_RV32 +endif + if BOARD_EMULATION_QEMU_RISCV config BOARD_SPECIFIC_OPTIONS diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig.name b/src/mainboard/emulation/qemu-riscv/Kconfig.name index e9243e6837..61fd919e7c 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig.name +++ b/src/mainboard/emulation/qemu-riscv/Kconfig.name @@ -1,2 +1,5 @@ -config BOARD_EMULATION_QEMU_RISCV - bool "QEMU riscv" +config BOARD_EMULATION_QEMU_RISCV_RV64 + bool "QEMU RISC-V rv64" + +config BOARD_EMULATION_QEMU_RISCV_RV32 + bool "QEMU RISC-V rv32" diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv/Kconfig index f8c98ab5b3..03046f723f 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig +++ b/src/mainboard/emulation/spike-riscv/Kconfig @@ -16,6 +16,7 @@ if BOARD_EMULATION_SPIKE_RISCV config BOARD_SPECIFIC_OPTIONS def_bool y + select ARCH_RISCV_RV64 select SOC_UCB_RISCV select BOARD_ROMSIZE_KB_4096 select DRIVERS_UART_8250MEM diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index aa352d932b..ad48c1cb76 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -1,5 +1,4 @@ config SOC_UCB_RISCV - select ARCH_RISCV_RV64 select ARCH_RISCV_S select ARCH_RISCV_U select ARCH_RISCV_PMP @@ -15,6 +14,8 @@ config SOC_UCB_RISCV if SOC_UCB_RISCV +if ARCH_RISCV_RV64 + config RISCV_ARCH string default "rv64imafd" @@ -27,6 +28,24 @@ config RISCV_CODEMODEL string default "medany" +endif + +if ARCH_RISCV_RV32 + +config RISCV_ARCH + string + default "rv32im" + +config RISCV_ABI + string + default "ilp32" + +config RISCV_CODEMODEL + string + default "medany" + +endif + config RISCV_WORKING_HARTID int default 0 |