diff options
| -rw-r--r-- | src/mainboard/asrock/h81m-hds/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/asrock/h81m-hds/bootblock.c | 50 | ||||
| -rw-r--r-- | src/mainboard/asrock/h81m-hds/romstage.c | 31 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/Kconfig | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/bootblock.c | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 5 |
7 files changed, 56 insertions, 37 deletions
diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc index 7c1bf9ecd4..de18bc5aa8 100644 --- a/src/mainboard/asrock/h81m-hds/Makefile.inc +++ b/src/mainboard/asrock/h81m-hds/Makefile.inc @@ -16,3 +16,4 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += bootblock.c diff --git a/src/mainboard/asrock/h81m-hds/bootblock.c b/src/mainboard/asrock/h81m-hds/bootblock.c new file mode 100644 index 0000000000..7a841b84aa --- /dev/null +++ b/src/mainboard/asrock/h81m-hds/bootblock.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); + const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Select HWM/LED functions instead of floppy functions. */ + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); + + /* Power RAM in S3 and let the PCH handle power failure actions. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + /* + * Don't know what's needed here, just set the same as the vendor + * firmware. + */ + pnp_set_logical_device(IR_DEV); + pnp_write_config(IR_DEV, 0xf1, 0x5c); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index a917722306..3af82f2907 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -23,8 +23,6 @@ #include <northbridge/intel/haswell/pei_data.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6776/nct6776.h> static const struct rcba_config_instruction rcba_config[] = { RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), @@ -41,35 +39,6 @@ static const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_config_superio(void) -{ - const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); - const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); - const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); - const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2); - - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); - - /* Select HWM/LED functions instead of floppy functions. */ - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); - - /* Power RAM in S3 and let the PCH handle power failure actions. */ - pnp_set_logical_device(ACPI_DEV); - pnp_write_config(ACPI_DEV, 0xe4, 0x70); - - /* - * Don't know what's needed here, just set the same as the vendor - * firmware. - */ - pnp_set_logical_device(IR_DEV); - pnp_write_config(IR_DEV, 0xf1, 0x5c); - - nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); -} - void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index e0c55d2f92..49466bc569 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -23,7 +23,7 @@ config NORTHBRIDGE_INTEL_HASWELL select POSTCAR_STAGE select POSTCAR_CONSOLE select C_ENVIRONMENT_BOOTBLOCK -# select BOOTBLOCK_CONSOLE TODO: route LPC + select BOOTBLOCK_CONSOLE if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index fd00f6c50e..04e0bc9909 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -46,6 +46,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c pch.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c +bootblock-y += early_pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c romstage-y += early_spi.c rcba.c pmutil.c diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 69fdd611d2..39e69257eb 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -79,4 +79,7 @@ void bootblock_early_southbridge_init(void) /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + pch_enable_lpc(); + mainboard_config_superio(); } diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index f615507dad..c36257747d 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -104,8 +104,6 @@ int early_pch_init(const void *gpio_map, { int wake_from_s3; - pch_enable_lpc(); - pch_enable_bars(); #if CONFIG(INTEL_LYNXPOINT_LP) @@ -113,9 +111,6 @@ int early_pch_init(const void *gpio_map, #else setup_pch_gpios(gpio_map); #endif - - mainboard_config_superio(); - pch_generic_setup(); /* Enable SMBus for reading SPDs. */ |