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-rw-r--r--src/cpu/amd/car/cache_as_ram.inc4
-rw-r--r--src/cpu/amd/car/disable_cache_as_ram.c62
-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c64
3 files changed, 64 insertions, 66 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index b4de775b02..d09934111b 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -270,8 +270,8 @@ clear_fixed_var_mtrr_out:
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif
- movl $REAL_XIP_ROM_BASE, %eax
- orl $MTRR_TYPE_WRBACK, %eax
+ movl $REAL_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $0x203, %ecx
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index 817d43e297..946b57bc93 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -2,45 +2,45 @@
/* be warned, this file will be used other cores and core 0 / node 0 */
static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
{
- __asm__ __volatile__ (
- /* We don't need cache as ram for now on */
- /* disable cache */
- "movl %%cr0, %%eax\n\t"
- "orl $(0x1<<30),%%eax\n\t"
- "movl %%eax, %%cr0\n\t"
+ __asm__ __volatile__ (
+ /* We don't need cache as ram for now on */
+ /* disable cache */
+ "movl %%cr0, %%eax\n\t"
+ "orl $(0x1<<30),%%eax\n\t"
+ "movl %%eax, %%cr0\n\t"
- /* clear sth */
- "movl $0x269, %%ecx\n\t" /* fix4k_c8000*/
- "xorl %%edx, %%edx\n\t"
- "xorl %%eax, %%eax\n\t"
+ /* clear sth */
+ "movl $0x269, %%ecx\n\t" /* fix4k_c8000*/
+ "xorl %%edx, %%edx\n\t"
+ "xorl %%eax, %%eax\n\t"
"wrmsr\n\t"
#if CONFIG_DCACHE_RAM_SIZE > 0x8000
"movl $0x268, %%ecx\n\t" /* fix4k_c0000*/
- "wrmsr\n\t"
+ "wrmsr\n\t"
#endif
- /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
- "movl $0xC0010010, %%ecx\n\t"
-// "movl $SYSCFG_MSR, %ecx\n\t"
- "rdmsr\n\t"
- "andl $(~(3<<18)), %%eax\n\t"
-// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
- "wrmsr\n\t"
+ /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
+ "movl $0xC0010010, %%ecx\n\t"
+// "movl $SYSCFG_MSR, %ecx\n\t"
+ "rdmsr\n\t"
+ "andl $(~(3<<18)), %%eax\n\t"
+// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
+ "wrmsr\n\t"
- /* Set the default memory type and disable fixed and enable variable MTRRs */
- "movl $0x2ff, %%ecx\n\t"
-// "movl $MTRRdefType_MSR, %ecx\n\t"
- "xorl %%edx, %%edx\n\t"
- /* Enable Variable and Disable Fixed MTRRs */
- "movl $0x00000800, %%eax\n\t"
- "wrmsr\n\t"
+ /* Set the default memory type and disable fixed and enable variable MTRRs */
+ "movl $0x2ff, %%ecx\n\t"
+// "movl $MTRRdefType_MSR, %ecx\n\t"
+ "xorl %%edx, %%edx\n\t"
+ /* Enable Variable and Disable Fixed MTRRs */
+ "movl $0x00000800, %%eax\n\t"
+ "wrmsr\n\t"
- /* enable cache */
- "movl %%cr0, %%eax\n\t"
- "andl $0x9fffffff,%%eax\n\t"
- "movl %%eax, %%cr0\n\t"
- ::: "memory", "eax", "ecx", "edx"
- );
+ /* enable cache */
+ "movl %%cr0, %%eax\n\t"
+ "andl $0x9fffffff,%%eax\n\t"
+ "movl %%eax, %%cr0\n\t"
+ ::: "memory", "eax", "ecx", "edx"
+ );
}
static void disable_cache_as_ram_bsp(void)
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 10194b9659..8ce49aa800 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -5,7 +5,7 @@
static inline void print_debug_pcar(const char *strval, uint32_t val)
{
- printk_debug("%s%08x\r\n", strval, val);
+ printk_debug("%s%08x\r\n", strval, val);
}
/* from linux kernel 2.6.32 asm/string_32.h */
@@ -41,15 +41,15 @@ static void post_cache_as_ram(void)
{
#if 1
- {
- /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
- unsigned v_esp;
- __asm__ volatile (
- "movl %%esp, %0\n\t"
- : "=a" (v_esp)
- );
- print_debug_pcar("v_esp=", v_esp);
- }
+ {
+ /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+ unsigned v_esp;
+ __asm__ volatile (
+ "movl %%esp, %0\n\t"
+ : "=a" (v_esp)
+ );
+ print_debug_pcar("v_esp=", v_esp);
+ }
#endif
unsigned testx = 0x5a5a5a5a;
@@ -59,7 +59,7 @@ static void post_cache_as_ram(void)
ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
*/
#if CONFIG_RAMTOP <= 0x100000
- #error "You need to set CONFIG_RAMTOP greater than 1M"
+ #error "You need to set CONFIG_RAMTOP greater than 1M"
#endif
/* So we can access RAM from [1M, CONFIG_RAMTOP) */
@@ -71,51 +71,49 @@ static void post_cache_as_ram(void)
/* from here don't store more data in CAR */
vErrata343();
- memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
-// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
+ memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
+// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
- __asm__ volatile (
- /* set new esp */ /* before CONFIG_RAMBASE */
- "subl %0, %%esp\n\t"
- ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
+ __asm__ volatile (
+ /* set new esp */ /* before CONFIG_RAMBASE */
+ "subl %0, %%esp\n\t"
+ ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
/* discard all registers (eax is used for %0), so gcc redo everything
after the stack is moved */
: "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp"
- );
+ );
/* We can put data to stack again */
- /* only global variable sysinfo in cache need to be offset */
- print_debug("Done\r\n");
- print_debug_pcar("testx = ", testx);
+ /* only global variable sysinfo in cache need to be offset */
+ print_debug("Done\r\n");
+ print_debug_pcar("testx = ", testx);
print_debug("Disabling cache as ram now \r\n");
disable_cache_as_ram_bsp();
- print_debug("Clearing initial memory region: ");
+ print_debug("Clearing initial memory region: ");
#if CONFIG_HAVE_ACPI_RESUME == 1
/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0);
#else
- memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
+ memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
#endif
- print_debug("Done\r\n");
+ print_debug("Done\r\n");
// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
- set_sysinfo_in_ram(1); // So other core0 could start to train mem
+ set_sysinfo_in_ram(1); // So other core0 could start to train mem
#if CONFIG_MEM_TRAIN_SEQ == 1
// struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- // wait for ap memory to trained
-// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
+ // wait for ap memory to trained
+// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
#endif
- /*copy and execute coreboot_ram */
- copy_and_run();
- /* We will not return */
-
- print_debug("should not be here -\r\n");
+ /*copy and execute coreboot_ram */
+ copy_and_run();
+ /* We will not return */
+ print_debug("should not be here -\r\n");
}
-
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 10:14:59 +0000