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-rw-r--r--src/soc/intel/common/acpi/gpio.asl19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/common/acpi/gpio.asl b/src/soc/intel/common/acpi/gpio.asl
new file mode 100644
index 0000000000..364ac73843
--- /dev/null
+++ b/src/soc/intel/common/acpi/gpio.asl
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/*
+ * Configure GPIO Power Management bits
+ *
+ * Arg0: GPIO community (0-5)
+ * Arg1: PM bits in MISCCFG
+ */
+Method (CGPM, 2, Serialized)
+{
+ Local0 = GPID (Arg0)
+ If (Local0 != 0) {
+ /* Mask off current PM bits */
+ PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ /* Mask in requested bits */
+ PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ }
+}