diff options
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 19 |
2 files changed, 19 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 48faf5fb73..c7afa115cb 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -108,8 +108,6 @@ static void sandybridge_setup_graphics(void) pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); /* Erratum workarounds */ - MCHBAR8(0x5f10) = 0x20; - reg32 = MCHBAR32(0x5f00); reg32 |= (1 << 9)|(1 << 10); MCHBAR32(0x5f00) = reg32; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index baf4348f96..bfb2166a11 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -388,9 +388,28 @@ static void northbridge_dmi_init(struct device *dev) static void northbridge_init(struct device *dev) { u8 bios_reset_cpl; + u32 bridge_type; northbridge_dmi_init(dev); + bridge_type = MCHBAR32(0x5f10); + bridge_type &= ~0xff; + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* Enable Power Aware Interrupt Routing */ + u8 pair = MCHBAR8(0x5418); + pair &= ~0xf; /* Clear 3:0 */ + pair |= 0x4; /* Fixed Priority */ + MCHBAR8(0x5418) = pair; + + /* 30h for IvyBridge */ + bridge_type |= 0x30; + } else { + /* 20h for Sandybridge */ + bridge_type |= 0x20; + } + MCHBAR32(0x5f10) = bridge_type; + /* * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU * that BIOS has initialized memory and power management |