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-rw-r--r--src/cpu/samsung/exynos5420/clock_init.c2
-rw-r--r--src/cpu/samsung/exynos5420/setup.h2
2 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c
index eeeda90bf2..15cd0c0368 100644
--- a/src/cpu/samsung/exynos5420/clock_init.c
+++ b/src/cpu/samsung/exynos5420/clock_init.c
@@ -209,6 +209,8 @@ void system_clock_init(void)
writel(CLK_DIV_PERIC3_VAL, &clk->clk_div_peric3);
writel(CLK_DIV_PERIC4_VAL, &clk->clk_div_peric4);
+ writel(CLK_DIV_CPERI1_VAL, &clk->clk_div_cperi1);
+
writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
writel(CLK_DIV_G2D, &clk->clk_div_g2d);
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 8f14a91602..ca7281dd82 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -48,6 +48,8 @@ struct exynos5_phy_control;
#define APLL_FOUT (1 << 0)
#define KPLL_FOUT (1 << 0)
+#define CLK_DIV_CPERI1_VAL 0x3f3f0000
+
/* APLL_CON1 */
#define APLL_CON1_VAL (0x0020f300)