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-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 3ab8e46098..fc081549f3 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -1342,14 +1342,11 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
Errors = 0;
dual_rank = 0;
- Receiver = mct_InitReceiver_D(pDCTstat, dct);
- if (receiver_start > Receiver)
- Receiver = receiver_start;
/* There are four receiver pairs, loosely associated with chipselects.
* This is essentially looping over each rank within each DIMM.
*/
- for (; Receiver < receiver_end; Receiver++) {
+ for (Receiver = receiver_start; Receiver < receiver_end; Receiver++) {
dimm = (Receiver >> 1);
if ((Receiver & 0x1) == 0) {
/* Even rank of DIMM */