diff options
| -rw-r--r-- | src/soc/mediatek/mt8173/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/bootblock.c | 3 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/mmu_operations.h | 35 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/mmu_operations.c | 68 |
4 files changed, 108 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 27ed312095..1b17d957cc 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -27,6 +27,7 @@ endif bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c bootblock-y += wdt.c +bootblock-y += mmu_operations.c ################################################################################ @@ -47,6 +48,7 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += cbmem.c romstage-y += spi.c romstage-y += gpio.c +romstage-y += mmu_operations.c ################################################################################ diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index 0b6d1ea979..7fe879c4b9 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -14,6 +14,7 @@ */ #include <bootblock_common.h> +#include <soc/mmu_operations.h> #include <soc/mt6391.h> #include <soc/pll.h> #include <soc/wdt.h> @@ -28,6 +29,8 @@ void bootblock_soc_init(void) /* post init pll */ mt_pll_post_init(); + mt8173_mmu_init(); + /* init watch dog, will disable AP watch dog */ mtk_wdt_init(); } diff --git a/src/soc/mediatek/mt8173/include/soc/mmu_operations.h b/src/soc/mediatek/mt8173/include/soc/mmu_operations.h new file mode 100644 index 0000000000..98fffa2758 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/mmu_operations.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ +#define __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ + +#include <arch/mmu.h> + +enum { + DEV_MEM = MA_DEV | MA_S | MA_RW, + CACHED_MEM = MA_MEM | MA_NS | MA_RW, + SECURE_MEM = MA_MEM | MA_S | MA_RW, + UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC, +}; + +extern unsigned char _sram_l2c[]; +extern unsigned char _esram_l2c[]; +#define _sram_l2c_size (_esram_l2c - _sram_l2c) + +void mt8173_mmu_init(void); +void mt8173_mmu_after_dram(void); + +#endif //__SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c new file mode 100644 index 0000000000..a70fe2ccaa --- /dev/null +++ b/src/soc/mediatek/mt8173/mmu_operations.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <arch/mmu.h> +#include <console/console.h> +#include <symbols.h> +#include <stdlib.h> +#include <stdint.h> +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/mcucfg.h> +#include <soc/mmu_operations.h> + +static const uint64_t dram_size = (uint64_t)CONFIG_DRAM_SIZE_MB * MiB; + +void mt8173_mmu_init(void) +{ + mmu_init(); + + /* Set 0x0 to end of dram as device memory */ + mmu_config_range((void *)0, (uintptr_t)_dram + dram_size, DEV_MEM); + + /* SRAM is cached */ + mmu_config_range(_sram_l2c, _sram_l2c_size + _sram_size, CACHED_MEM); + + /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ + mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); + + /* set ttb as secure */ + mmu_config_range(_ttb, _ttb_size, SECURE_MEM); + + mmu_enable(); +} + +void mt8173_mmu_after_dram(void) +{ + /* Remap DRAM as cached now that it's up and running */ + mmu_config_range(_dram, dram_size, CACHED_MEM); + + /* Unmap L2C SRAM so it can be reclaimed by L2 cache */ + /* TODO: Implement true unmapping, and also use it for the zero-page! */ + mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM); + + /* Careful: changing cache geometry while it's active is a bad idea! */ + mmu_disable(); + + /* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max + * available L2 cache for A53 in MT8173. */ + write32(&mt8173_mcucfg->mp0_ca7l_cache_config, 3 << 8); + /* turn off the l2c sram clock */ + write32(&mt8173_infracfg->infra_pdn0, L2C_SRAM_PDN); + + /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */ + mmu_enable(); +} |