diff options
| -rw-r--r-- | src/mainboard/lenovo/x201/romstage.c | 22 | ||||
| -rw-r--r-- | src/mainboard/packardbell/ms2290/romstage.c | 17 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/romstage.c | 26 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/early_pch.c | 93 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 20 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 2 |
7 files changed, 98 insertions, 83 deletions
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 1440c19573..81752e88ae 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -26,28 +26,6 @@ void mainboard_lpc_init(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN | GAMEL_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); - pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); - - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); - - pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); - /* Enable USB Power. We need to do it early for usbdebug to work. */ ec_set_bit(0x3b, 4); } diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index b25676bf53..61e14f20e3 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -24,23 +24,6 @@ void mainboard_lpc_init(void) { - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x00040001); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); - pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); - - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); - - pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); } /* Seems copied from Lenovo Thinkpad x201, might be wrong */ diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c index 83848273a0..c465a99365 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/nehalem/romstage.c @@ -30,8 +30,6 @@ #include <northbridge/intel/nehalem/raminit.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/me.h> -#include <southbridge/intel/common/pmclib.h> -#include <southbridge/intel/common/gpio.h> /* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. @@ -47,29 +45,7 @@ void mainboard_romstage_entry(void) /* TODO, make this configurable */ nehalem_early_initialization(NEHALEM_MOBILE); - /* mainboard_lpc_init */ - mainboard_lpc_init(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* TODO, make this configurable */ - pch_setup_cir(NEHALEM_MOBILE); - - southbridge_configure_default_intmap(); - - /* Must set BIT0 (hides performance counters PCI device). - coreboot enables the Rate Matching Hub which makes the UHCI PCI - devices disappear, so BIT5-12 and BIT28 can be set to hide those. */ - RCBA32(FD) = (1 << 28) | (0xff << 5) | 1; - - /* Set reserved bit to 1 */ - RCBA32(FD2) = 1; - - early_usb_init(mainboard_usb_ports); + early_pch_init(); /* Initialize console device(s) */ console_init(); diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index f22be2453b..8c4443ce0e 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += madt.c smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c +romstage-y += early_pch.c romstage-y += early_smbus.c romstage-y +=../bd82x6x/early_me.c romstage-y +=../bd82x6x/me_status.c diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c new file mode 100644 index 0000000000..2707eb2cb8 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> + * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/pci_ops.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/common/gpio.h> + +#include "chip.h" + +static void early_lpc_init(void) +{ + const struct device *dev = pcidev_on_root(0x1f, 0); + const struct southbridge_intel_ibexpeak_config *config = NULL; + + /* Add some default decode ranges: + - 0x2e/2f, 0x4e/0x4f + - EC/Mouse/KBC 60/64, 62/66 + - 0x3f8 COMA + If more are needed, update in mainboard_lpc_init hook + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + /* Clear PWR_FLR */ + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, + (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); + + pci_write_config32(PCH_LPC_DEV, ETR3, + pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); + + /* Set up generic decode ranges */ + if (!dev) + return; + if (dev->chip_info) + config = dev->chip_info; + if (!config) + return; + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); +} + +static void early_gpio_init(void) +{ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); +} + +static void pch_default_disable(void) +{ + /* Must set BIT0 (hides performance counters PCI device). + coreboot enables the Rate Matching Hub which makes the UHCI PCI + devices disappear, so BIT5-12 and BIT28 can be set to hide those. */ + RCBA32(FD) = (1 << 28) | (0xff << 5) | 1; + + /* Set reserved bit to 1 */ + RCBA32(FD2) = 1; +} + +void early_pch_init(void) +{ + early_lpc_init(); + mainboard_lpc_init(); + early_gpio_init(); + /* TODO, make this configurable */ + pch_setup_cir(NEHALEM_MOBILE); + southbridge_configure_default_intmap(); + pch_default_disable(); + early_usb_init(mainboard_usb_ports); +} diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e433530bae..a457722ac8 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -465,18 +465,6 @@ static void pch_fixups(struct device *dev) RCBA32_OR(0x21a8, 0x3); } -static void pch_decode_init(struct device *dev) -{ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "pch_decode_init\n"); - - pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); -} - static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n"); @@ -587,12 +575,6 @@ static void pch_lpc_read_resources(struct device *dev) } } -static void pch_lpc_enable_resources(struct device *dev) -{ - pch_decode_init(dev); - return pci_dev_enable_resources(dev); -} - static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ @@ -794,7 +776,7 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pch_lpc_enable_resources, + .enable_resources = pci_dev_enable_resources, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index fbe88a5d7c..b9632371ac 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -62,6 +62,8 @@ int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); #endif +void early_pch_init(void); + void early_thermal_init(void); void southbridge_configure_default_intmap(void); void pch_setup_cir(int chipset_type); |