diff options
| -rw-r--r-- | src/mainboard/arima/hdama/auto.c | 331 | ||||
| -rw-r--r-- | src/mainboard/arima/hdama/mainboard.c | 126 | ||||
| -rw-r--r-- | src/mainboard/arima/hdama/mptable.c | 224 |
3 files changed, 465 insertions, 216 deletions
diff --git a/src/mainboard/arima/hdama/auto.c b/src/mainboard/arima/hdama/auto.c index 94ce39d464..750710f92a 100644 --- a/src/mainboard/arima/hdama/auto.c +++ b/src/mainboard/arima/hdama/auto.c @@ -7,6 +7,111 @@ #include "ram/ramtest.c" #include "northbridge/amd/amdk8/early_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" + +#warning "FIXME move these delay functions somewhere more appropriate" +#warning "FIXME use the apic timer instead it needs no calibration on an Opteron it runs at 200Mhz" +static void print_clock_multiplier(void) +{ + msr_t msr; + print_debug("clock multipler: 0x"); + msr = rdmsr(0xc0010042); + print_debug_hex32(msr.lo & 0x3f); + print_debug(" = 0x"); + print_debug_hex32(((msr.lo & 0x3f) + 8) * 100); + print_debug("Mhz\r\n"); +} + +static unsigned usecs_to_ticks(unsigned usecs) +{ +#warning "FIXME make usecs_to_ticks work properly" +#if 1 + return usecs *2000; +#else + /* This can only be done if cpuid says fid changing is supported + * I need to look up the base frequency another way for other + * cpus. Is it worth dedicating a global register to this? + * Are the PET timers useable for this purpose? + */ + msr_t msr; + msr = rdmsr(0xc0010042); + return ((msr.lo & 0x3f) + 8) * 100 *usecs; +#endif +} + +static void init_apic_timer(void) +{ + volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000; + uint32_t start, end; + /* Set the apic timer to no interrupts and periodic mode */ + apic_reg[0x320 >> 2] = (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0); + /* Set the divider to 1, no divider */ + apic_reg[0x3e0 >> 2] = (1 << 3) | 3; + /* Set the initial counter to 0xffffffff */ + apic_reg[0x380 >> 2] = 0xffffffff; +} + +static void udelay(unsigned usecs) +{ +#if 1 + uint32_t start, ticks; + tsc_t tsc; + /* Calculate the number of ticks to run for */ + ticks = usecs_to_ticks(usecs); + /* Find the current time */ + tsc = rdtsc(); + start = tsc.lo; + do { + tsc = rdtsc(); + } while((tsc.lo - start) < ticks); +#else + volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000; + uint32_t start, value, ticks; + /* Calculate the number of ticks to run for */ + ticks = usecs * 200; + start = apic_reg[0x390 >> 2]; + do { + value = apic_reg[0x390 >> 2]; + } while((start - value) < ticks); +#endif +} + +static void mdelay(unsigned msecs) +{ + int i; + for(i = 0; i < msecs; i++) { + udelay(1000); + } +} + +static void delay(unsigned secs) +{ + int i; + for(i = 0; i < secs; i++) { + mdelay(1000); + } +} + + +static void memreset_setup(const struct mem_controller *ctrl) +{ + /* Set the memreset low */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + print_debug("memreset lo\r\n"); +} + +static void memreset(const struct mem_controller *ctrl) +{ + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + print_debug("memreset hi\r\n"); + udelay(50); +} + + #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" @@ -27,9 +132,7 @@ static int boot_cpu(void) msr = rdmsr(0x1b); bsp = !!(msr.lo & (1 << 8)); if (bsp) { - print_debug("Bootstrap processor\r\n"); - } else { - print_debug("Application processor\r\n"); + print_debug("Bootstrap cpu\r\n"); } return bsp; @@ -116,67 +219,221 @@ static void dump_pci_device(unsigned dev) } } -static void dump_spd_registers(void) +static void dump_pci_devices(void) { - unsigned device; - device = SMBUS_MEM_DEVICE_START; + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} + +static void dump_spd_registers(const struct mem_controller *ctrl) +{ + int i; print_debug("\r\n"); - while(device <= SMBUS_MEM_DEVICE_END) { - int i; - print_debug("dimm: "); - print_debug_hex8(device); - for(i = 0; i < 256; i++) { - int status; - unsigned char byte; - if ((i & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(i); - print_debug(": "); + for(i = 0; i < 4; i++) { + unsigned device; + device = ctrl->channel0[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); } - status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device\r\n"); - break; + print_debug("\r\n"); + } + device = ctrl->channel1[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".1: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); + print_debug("\r\n"); } - device += SMBUS_MEM_DEVICE_INC; - print_debug("\r\n"); } } +static void pnp_write_config(unsigned char port, unsigned char value, unsigned char reg) +{ + outb(reg, port); + outb(value, port +1); +} + +static unsigned char pnp_read_config(unsigned char port, unsigned char reg) +{ + outb(reg, port); + return inb(port +1); +} + +static void pnp_set_logical_device(unsigned char port, int device) +{ + pnp_write_config(port, device, 0x07); +} + +static void pnp_set_enable(unsigned char port, int enable) +{ + pnp_write_config(port, enable?0x1:0x0, 0x30); +} + +static int pnp_read_enable(unsigned char port) +{ + return !!pnp_read_config(port, 0x30); +} + +static void pnp_set_iobase0(unsigned char port, unsigned iobase) +{ + pnp_write_config(port, (iobase >> 8) & 0xff, 0x60); + pnp_write_config(port, iobase & 0xff, 0x61); +} + +static void pnp_set_iobase1(unsigned char port, unsigned iobase) +{ + pnp_write_config(port, (iobase >> 8) & 0xff, 0x62); + pnp_write_config(port, iobase & 0xff, 0x63); +} + +static void pnp_set_irq0(unsigned char port, unsigned irq) +{ + pnp_write_config(port, irq, 0x70); +} + +static void pnp_set_irq1(unsigned char port, unsigned irq) +{ + pnp_write_config(port, irq, 0x72); +} + +static void pnp_set_drq(unsigned char port, unsigned drq) +{ + pnp_write_config(port, drq & 0xff, 0x74); +} + +#define PC87360_FDC 0x00 +#define PC87360_PP 0x01 +#define PC87360_SP2 0x02 +#define PC87360_SP1 0x03 +#define PC87360_SWC 0x04 +#define PC87360_KBCM 0x05 +#define PC87360_KBCK 0x06 +#define PC87360_GPIO 0x07 +#define PC87360_ACB 0x08 +#define PC87360_FSCM 0x09 +#define PC87360_WDT 0x0A + +static void pc87360_enable_serial(void) +{ + pnp_set_logical_device(SIO_BASE, PC87360_SP1); + pnp_set_enable(SIO_BASE, 1); + pnp_set_iobase0(SIO_BASE, 0x3f8); +} static void main(void) { + /* + * GPIO28 of 8111 will control H0_MEMRESET_L + * GPIO29 of 8111 will control H1_MEMRESET_L + */ + + static const struct mem_controller cpu0 = { + .f0 = PCI_DEV(0, 0x18, 0), + .f1 = PCI_DEV(0, 0x18, 1), + .f2 = PCI_DEV(0, 0x18, 2), + .f3 = PCI_DEV(0, 0x18, 3), + .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, + .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + .memreset = 28, + }; + static const struct mem_controller cpu1 = { + .f0 = PCI_DEV(0, 0x19, 0), + .f1 = PCI_DEV(0, 0x19, 1), + .f2 = PCI_DEV(0, 0x19, 2), + .f3 = PCI_DEV(0, 0x19, 3), + .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, + .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + .memreset = 29, + }; + pc87360_enable_serial(); uart_init(); console_init(); -#if 0 - print_debug(" XIP_ROM_BASE: "); - print_debug_hex32(XIP_ROM_BASE); - print_debug(" XIP_ROM_SIZE: "); - print_debug_hex32(XIP_ROM_SIZE); - print_debug("\r\n"); -#endif if (boot_cpu() && !cpu_init_detected()) { +#if 1 + init_apic_timer(); +#endif setup_default_resource_map(); setup_coherent_ht_domain(); enumerate_ht_chain(); print_pci_devices(); enable_smbus(); - sdram_initialize(); + dump_spd_registers(&cpu0); + sdram_initialize(&cpu0); - dump_spd_registers(); +#if 0 + dump_pci_devices(); +#endif +#if 0 dump_pci_device(PCI_DEV(0, 0x18, 2)); - - /* Check the first 512M */ +#endif + + /* Check all of memory */ msr_t msr; msr = rdmsr(TOP_MEM); print_debug("TOP_MEM: "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\r\n"); +#if 0 ram_check(0x00000000, msr.lo); +#else + /* Check 16MB of memory */ + ram_check(0x00000000, 0x1600000); +#endif +#if 0 + print_debug("sleeping 15s\r\n"); + delay(15); + print_debug("sleeping 15s done\r\n"); +#endif } } diff --git a/src/mainboard/arima/hdama/mainboard.c b/src/mainboard/arima/hdama/mainboard.c index 6578ef606f..5690bd5afd 100644 --- a/src/mainboard/arima/hdama/mainboard.c +++ b/src/mainboard/arima/hdama/mainboard.c @@ -9,129 +9,3 @@ unsigned long initial_apicid[MAX_CPUS] = { 0 }; - -void -mainboard_fixup(void) -{ -} - -void -final_mainboard_fixup(void) -{ -#if 0 -// void final_southbridge_fixup(void); -// void final_superio_fixup(void); - - printk_info("AMD Solo initializing..."); - -// final_southbridge_fixup(); - -//#ifndef USE_NEW_SUPERIO_INTERFACE -//final_superio_fixup(); -//#endif -#endif -} - -struct ioapicreg { - unsigned int reg; - unsigned int value_low, value_high; -}; -static struct ioapicreg ioapicregvalues[] = { -#define ALL (0xff << 24) -#define NONE (0) -#define DISABLED (1 << 16) -#define ENABLED (0 << 16) -#define TRIGGER_EDGE (0 << 15) -#define TRIGGER_LEVEL (1 << 15) -#define POLARITY_HIGH (0 << 13) -#define POLARITY_LOW (1 << 13) -#define PHYSICAL_DEST (0 << 11) -#define LOGICAL_DEST (1 << 11) -#define ExtINT (7 << 8) -#define NMI (4 << 8) -#define SMI (2 << 8) -#define INT (1 << 8) - /* mask, trigger, polarity, destination, delivery, vector */ - {0x00, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT | 0, 0}, - {0x01, DISABLED, NONE}, - {0x02, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | INT | 0, 0}, - {0x03, DISABLED, NONE}, - {0x04, DISABLED, NONE}, - {0x05, DISABLED, NONE}, - {0x06, DISABLED, NONE}, - {0x07, DISABLED, NONE}, - {0x08, DISABLED, NONE}, - {0x09, DISABLED, NONE}, - {0x0a, DISABLED, NONE}, - {0x0b, DISABLED, NONE}, - {0x0c, DISABLED, NONE}, - {0x0d, DISABLED, NONE}, - {0x0e, DISABLED, NONE}, - {0x0f, DISABLED, NONE}, - {0x10, DISABLED, NONE}, - {0x11, DISABLED, NONE}, - {0x12, DISABLED, NONE}, - {0x13, DISABLED, NONE}, - {0x14, DISABLED, NONE}, - {0x14, DISABLED, NONE}, - {0x15, DISABLED, NONE}, - {0x16, DISABLED, NONE}, - {0x17, DISABLED, NONE}, - {0x18, DISABLED, NONE}, - {0x19, DISABLED, NONE}, - {0x20, DISABLED, NONE}, - {0x21, DISABLED, NONE}, - {0x22, DISABLED, NONE}, - {0x23, DISABLED, NONE}, -}; - -static void setup_ioapic(void) -{ - int i; - unsigned long value_low, value_high; - unsigned long ioapic_base = 0xfec00000; - volatile unsigned long *l; - struct ioapicreg *a = ioapicregvalues; - - l = (unsigned long *) ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); - i++, a++) { - l[0] = (a->reg * 2) + 0x10; - l[4] = a->value_low; - value_low = l[4]; - l[0] = (a->reg *2) + 0x11; - l[4] = a->value_high; - value_high = l[4]; - if ((i==0) && (value_low == 0xffffffff)) { - printk_warning("IO APIC not responding.\n"); - return; - } - printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n", - a->reg, a->value_low, a->value_high); - } -} - -static void lpc_init(struct device *dev) -{ - uint8_t byte; - printk_debug("lpc_init\n"); -#if 0 - pci_read_config_byte(dev, 0x4B, &byte); - byte |= 1; - pci_write_config_byte(dev, 0x4B, byte); - setup_ioapic(); -#endif -} - -static struct device_operations lpc_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .init = lpc_init, - .scan_bus = 0, -}; - -static struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7468, -}; diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 656b790035..faf0711b17 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -8,8 +8,13 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) { static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; - static const char productid[12] = "P4DPR "; + static const char productid[12] = "HDAMA "; struct mp_config_table *mc; + unsigned char bus_num; + unsigned char bus_isa; + unsigned char bus_8131_1; + unsigned char bus_8131_2; + unsigned char bus_8111_1; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -30,79 +35,192 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) smp_write_processors(mc, processor_map); - smp_write_bus(mc, 0, "PCI "); - smp_write_bus(mc, 1, "PCI "); - smp_write_bus(mc, 2, "PCI "); - smp_write_bus(mc, 3, "ISA "); + { + struct pci_dev *dev; + uint32_t base; + /* 8111 */ + dev = dev_find_slot(0, PCI_DEVFN(0x03,0)); + if (dev) { + bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + else { + printk_debug("ERROR - could not find PCI 0:03.0, using defaults\n"); + + bus_8111_1 = 3; + bus_isa = 4; + } + /* 8131-1 */ + dev = dev_find_slot(0, PCI_DEVFN(0x01,0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 0:01.0, using defaults\n"); + + bus_8131_1 = 1; + } + /* 8131-2 */ + dev = dev_find_slot(0, PCI_DEVFN(0x02,0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 0:02.0, using defaults\n"); + + bus_8131_2 = 2; + } + } + + /* define bus and isa numbers */ + for(bus_num = 0; bus_num < bus_isa; bus_num++) { + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, bus_isa, "ISA "); + + /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x11, 0xfec00000); + { + struct pci_dev *dev; + uint32_t base; + /* 8131 apic 3 */ + dev = dev_find_slot(0, PCI_DEVFN(0x01,1)); + if (dev) { + base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 3, 0x11, base); + } + /* 8131 apic 4 */ + dev = dev_find_slot(0, PCI_DEVFN(0x02,1)); + if (dev) { + base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 4, 0x11, base); + } + } /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x00, 0x02, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x01, 0x02, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x00, 0x02, 0x02); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x03, 0x02, 0x03); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x04, 0x02, 0x04); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x03, 0x05, 0x02, 0x05); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x06, 0x02, 0x06); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x07, 0x02, 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x03, 0x08, 0x02, 0x08); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x09, 0x02, 0x09); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x03, 0x0a, 0x02, 0x0a); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x03, 0x0b, 0x02, 0x0b); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x0c, 0x02, 0x0c); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x0d, 0x02, 0x0d); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x0e, 0x02, 0x0e); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x0f, 0x02, 0x0f); + bus_isa, 0x00, 0x02, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x01, 0x02, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x00, 0x02, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x03, 0x02, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x04, 0x02, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x05, 0x02, 0x05); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x06, 0x02, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x07, 0x02, 0x07); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x08, 0x02, 0x08); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x09, 0x02, 0x09); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x0a, 0x02, 0x0a); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x0b, 0x02, 0x0b); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x0c, 0x02, 0x0c); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x0d, 0x02, 0x0d); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x0e, 0x02, 0x0e); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x0f, 0x02, 0x0f); /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x03, 0x00, MP_APIC_ALL, 0x00); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x00, 0x00, MP_APIC_ALL, 0x01); + bus_isa, 0x00, MP_APIC_ALL, 0x00); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_isa, 0x00, MP_APIC_ALL, 0x01); - /* 8111 DevB.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x00, (5<<2)|3, 0x02, 0x13); - /* AGP Slot */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x01, (0<<2)|0, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x03, (6<<2)|0, 0x02, 0x12); /* PCI Slot 1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_2, (1<<2)|0, 0x04, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_2, (1<<2)|1, 0x04, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_2, (1<<2)|2, 0x04, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_2, (1<<2)|3, 0x04, 0x10); + /* PCI Slot 2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x02, (5 <<2)|0, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_2, (2<<2)|0, 0x04, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_2, (2<<2)|1, 0x04, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_2, (2<<2)|2, 0x04, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_2, (2<<2)|3, 0x04, 0x11); + /* PCI Slot 3 */ - /* PCI Slot 4 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x02, (7<<2)|0, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_1, (1<<2)|0, 0x03, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_1, (1<<2)|1, 0x03, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_1, (1<<2)|2, 0x03, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_1, (1<<2)|3, 0x03, 0x10); - /* AMR Slot */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - 0x02, (1<<2)|0, 0x02, 0x10); + /* PCI Slot 4 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_1, (2<<2)|0, 0x03, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_1, (2<<2)|1, 0x03, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_1, (2<<2)|2, 0x03, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_1, (2<<2)|3, 0x03, 0x11); + + /* PCI Slot 5 */ +#warning "FIXME get the irqs right, it's just hacked to work for now" + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8111_1, (5<<2)|0, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8111_1, (5<<2)|1, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8111_1, (5<<2)|2, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8111_1, (5<<2)|3, 0x02, 0x10); + + /* PCI Slot 6 */ +#warning "FIXME get the irqs right, it's just hacked to work for now" + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8111_1, (4<<2)|0, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8111_1, (4<<2)|1, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8111_1, (4<<2)|2, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8111_1, (4<<2)|3, 0x02, 0x13); + + /* On board nics */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_1, (3<<2)|0, 0x03, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + bus_8131_1, (4<<2)|0, 0x03, 0x10); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); |