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-rw-r--r--src/mainboard/razer/Kconfig17
-rw-r--r--src/mainboard/razer/Kconfig.name2
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/Kconfig55
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/Kconfig.name2
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/Makefile.inc22
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl30
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl119
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl105
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl52
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/acpi/superio.asl0
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/acpi_tables.c0
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/board_info.txt8
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/devicetree.cb277
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/dsdt.asl49
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads30
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/gpio.h182
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/hda_verb.c49
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/mainboard.c48
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/ramstage.c25
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/romstage.c63
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc21
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex16
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex16
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/spd/spd.h30
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c50
25 files changed, 1268 insertions, 0 deletions
diff --git a/src/mainboard/razer/Kconfig b/src/mainboard/razer/Kconfig
new file mode 100644
index 0000000000..bae422eaaa
--- /dev/null
+++ b/src/mainboard/razer/Kconfig
@@ -0,0 +1,17 @@
+
+if VENDOR_RAZER
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/razer/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/razer/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string "Mainboard Vendor"
+ default "RAZER"
+
+endif
diff --git a/src/mainboard/razer/Kconfig.name b/src/mainboard/razer/Kconfig.name
new file mode 100644
index 0000000000..8f67e02429
--- /dev/null
+++ b/src/mainboard/razer/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_RAZER
+ bool "RAZER"
diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig
new file mode 100644
index 0000000000..986a4df7bf
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig
@@ -0,0 +1,55 @@
+if BOARD_RAZER_BLADE_STEALTH_KBL
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+ select BOARD_ROMSIZE_KB_8192
+ select SUPERIO_ITE_IT8528E
+ select SOC_INTEL_KABYLAKE
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select MAINBOARD_USES_FSP2_0
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM2
+ select MAINBOARD_HAS_LIBGFXINIT
+ select GENERIC_SPD_BIN
+ select DRIVERS_I2C_HID
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select ADD_FSP_BINARIES
+ select FSP_USE_REPO
+ select NO_POST
+
+ # For now no way to choose the correct the available RAM
+ config BOARD_RAZER_BLADE_STEALTH_KBL_16GB
+ bool "16GB RAM (4x MT52L1G32D4PG)"
+ default n
+
+ config VGA_BIOS_ID
+ string
+ default "8086,5916"
+
+ config IRQ_SLOT_COUNT
+ int
+ default 18
+
+ config MAINBOARD_FAMILY
+ string
+ default "BLADE_STEALTH"
+
+ config MAINBOARD_PART_NUMBER
+ string
+ default "H2U"
+
+ config MAINBOARD_VERSION
+ string
+ default "1.0"
+
+ config MAINBOARD_DIR
+ string
+ default "razer/blade_stealth_kbl"
+
+ config MAX_CPUS
+ int
+ default 4
+
+endif
diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig.name b/src/mainboard/razer/blade_stealth_kbl/Kconfig.name
new file mode 100644
index 0000000000..5193f4089c
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_RAZER_BLADE_STEALTH_KBL
+ bool "Razer Blade Stealth KabyLake (2016)"
diff --git a/src/mainboard/razer/blade_stealth_kbl/Makefile.inc b/src/mainboard/razer/blade_stealth_kbl/Makefile.inc
new file mode 100644
index 0000000000..e517484499
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+ramstage-y += mainboard.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl
new file mode 100644
index 0000000000..813c008e68
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Johanna Schander <coreboot@mimoja.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (AC)
+{
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package () { \_SB })
+
+ Method (_PSR)
+ {
+ Return (ACEX)
+ }
+
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl
new file mode 100644
index 0000000000..a89496d69e
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Johanna Schander <coreboot@mimoja.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (BAT)
+{
+ Name (_HID, EisaId ("PNP0C0A"))
+ Name (_UID, 1)
+ Name (_PCL, Package () { \_SB })
+
+ Name (BSTP, 0)
+
+ Name (PBIF, Package () {
+ 0x00000001, /* 0x00: Power Unit: mAh */
+ 0xFFFFFFFF, /* 0x01: Design Capacity */
+ 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */
+ 0x00000001, /* 0x03: Battery Technology: Rechargeable */
+ 0xFFFFFFFF, /* 0x04: Design Voltage */
+ 0x00000003, /* 0x05: Design Capacity of Warning */
+ 0xFFFFFFFF, /* 0x06: Design Capacity of Low */
+ 0x00000001, /* 0x07: Capacity Granularity 1 */
+ 0x00000001, /* 0x08: Capacity Granularity 2 */
+ "Razer Blade Stealth",
+ "SERIAL",
+ "LiIon",
+ "Razer"
+ })
+
+
+ Name (PBST, Package () {
+ 0x00000000, /* 0x00: Battery State */
+ 0xFFFFFFFF, /* 0x01: Battery Present Rate */
+ 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */
+ 0xFFFFFFFF, /* 0x03: Battery Present Voltage */
+ })
+
+ Method (_STA, 0, Serialized)
+ {
+ Return (0x1F)
+ }
+
+ Method (_BIF, 0, Serialized)
+ {
+ /* Last Full Charge Capacity */
+ Store (BFCP, Index (PBIF, 2))
+
+ /* Design Voltage */
+ Store (BDVT, Index (PBIF, 4))
+
+ /* Design Capacity */
+ Store (BDCP, Index (PBIF, 1))
+
+ /* Design Capacity of Warning */
+ Store (BDCP / 0x32, Index (PBIF, 5))
+
+ /* Design Capacity of Low */
+ Store (BDCP / 0x64, Index (PBIF, 6))
+
+ Store (ToString (BSER, Ones), Index (PBIF, 0x0A))
+
+ Return (PBIF)
+ }
+
+ Method (_BST, 0, Serialized)
+ {
+ /*
+ * 0: BATTERY STATE
+ *
+ * bit 0 = discharging
+ * bit 1 = charging
+ * bit 2 = critical level
+ */
+
+ /* Check if AC is present */
+ If (ACEX) {
+ /* Read battery status from EC */
+ Store (BCST, Local0)
+ } Else {
+ /* Always discharging when on battery power */
+ Store (0x01, Local0)
+ }
+
+ Store (Local0, Index (PBST, 0))
+
+ /* Notify if battery state has changed since last time */
+ If (LNotEqual (Local0, BSTP)) {
+ Store (Local0, BSTP)
+ Notify (BAT, 0x80)
+ }
+
+ /*
+ * 1: BATTERY PRESENT RATE
+ */
+ Store (BCRT, Index (PBST, 1))
+
+ /*
+ * 2: BATTERY REMAINING CAPACITY
+ */
+ Store (BRCP, Index (PBST, 2))
+
+ /*
+ * 3: BATTERY PRESENT VOLTAGE
+ */
+ Store (BCVT, Index (PBST, 3))
+
+ Return (PBST)
+ }
+}
diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl
new file mode 100644
index 0000000000..62a8622dc1
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Johanna Schander <coreboot@mimoja.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (EC)
+{
+ Name (_HID, EisaId ("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 0x50) // Copied over
+
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+
+ Name (ACEX, 0)
+
+ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF)
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x1C),
+ ODP1, 8,
+ ODP2, 8,
+ Offset (0x56),
+ CPUT, 8,
+ CPU1, 8,
+ GPUT, 8,
+ ADPV, 16,
+ ADPC, 16,
+ FANC, 8,
+ Offset (0x60),
+ BSER, 256, // BAT Serial Number
+ Offset (0x90),
+ BIF0, 16,
+ BDCP, 16, // BAT Design Capacity
+ BFCP, 16, // BAT Full Capacity
+ BRCH, 16, // BAT Rechargable
+ BDVT, 16, // BAT Design Voltage
+ BIF5, 16,
+ BIF6, 16,
+ BIF7, 16,
+ BIF8, 16,
+ BCST, 16, // BAT Current State
+ BCRT, 16, // BAT Current Rate
+ BRCP, 16, // BAT Remaining Capacity
+ BCVT, 16, // BAT Current Voltage
+ PWRS, 8, // Power State (?)
+ ECN0, 8,
+ Offset (0xB0),
+ SRNM, 16,
+ MFDA, 16,
+ PHMR, 8,
+ BLDA, 8,
+ Offset (0xE2),
+ LIDS, 8 // Lid state
+ }
+
+ Method (_REG, 2, NotSerialized)
+ {
+ /* Initialize AC power state */
+ Store (PWRS - 0x82, ACEX)
+
+ /* Initialize LID switch state */
+ Store (LIDS, \LIDS)
+ }
+
+
+ // Close ?
+ Method (_Q14, 0, NotSerialized)
+ {
+ Store (LIDS, \LIDS)
+ Notify (LID0, 0x80)
+ }
+
+ //Open
+ Method (_Q15, 0, NotSerialized)
+ {
+ Store (LIDS, \LIDS)
+ Notify (LID0, 0x80)
+ }
+
+
+ // AC plugged
+ Method (_Q13, 0, NotSerialized)
+ {
+ Store (PWRS - 0x82, ACEX)
+ Notify (BAT, 0x80) // Status Change
+ Notify (BAT, 0x81) // Information Change
+ Notify (AC, 0x80) // Status Change
+ }
+
+ #include "ac.asl"
+ #include "battery.asl"
+}
diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl
new file mode 100644
index 0000000000..6b8cb51380
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+
+ Method (_LID)
+ {
+ if (\_SB.PCI0.LPCB.EC.LIDS > 1)
+ {
+ Return (One)
+ }
+ else
+ {
+ Return (Zero)
+ }
+ }
+
+ Method (_STA)
+ {
+ Return (_LID)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+
+ Name (_PRW, Package () { 27, 4 })
+ }
+
+}
diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/superio.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/acpi/superio.asl
diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi_tables.c b/src/mainboard/razer/blade_stealth_kbl/acpi_tables.c
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/acpi_tables.c
diff --git a/src/mainboard/razer/blade_stealth_kbl/board_info.txt b/src/mainboard/razer/blade_stealth_kbl/board_info.txt
new file mode 100644
index 0000000000..414d880a12
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: RAZER
+Board name: Blade Stealth KabyLake (H2U)
+Category: laptop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2016
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
new file mode 100644
index 0000000000..deb98690f8
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -0,0 +1,277 @@
+chip soc/intel/skylake
+ # Enable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ register "eist_enable" = "1"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ register "gen1_dec" = "0x000c0081"
+ register "gen2_dec" = "0x000c0681"
+ register "gen3_dec" = "0x000c1641"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "0"
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "0"
+ register "SataPortsEnable[1]" = "0"
+ register "SataPortsEnable[2]" = "0"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "0"
+ register "IoBufferOwnership" = "0"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "PttSwitch" = "0"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "1"
+ register "SaGv" = "SaGv_Enabled"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "0"
+
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 6A | 64A | 31A | 31A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-----------+-----------+-------------+----------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 0,
+ .psi4enable = 0,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(6),
+ .voltage_limit = 1520,
+ .ac_loadline = 1030,
+ .dc_loadline = 1030,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 0,
+ .psi4enable = 0,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(64),
+ .voltage_limit = 1520,
+ .ac_loadline = 240,
+ .dc_loadline = 240,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 0,
+ .psi4enable = 0,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(31),
+ .voltage_limit = 1520,
+ .ac_loadline = 310,
+ .dc_loadline = 310,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 0,
+ .psi4enable = 0,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(31),
+ .voltage_limit = 1520,
+ .ac_loadline = 310,
+ .dc_loadline = 310,
+ }"
+
+ # Enable Root Ports 3, 5 and 9
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpEnable[8]" = "1"
+
+ register "PcieRpLtrEnable[2]" = "1"
+ register "PcieRpLtrEnable[4]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+
+ register "PcieRpHotPlug[4]" = "1"
+
+ # USB
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
+
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC?
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC?
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC?
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC?
+
+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Camera
+ register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # Keyboard
+ register "usb2_ports[8]" = "USB2_PORT_FLEX(OC2)" # Touchscreen
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
+
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC?
+
+ # PL1 override 25W
+ register "tdp_pl1_override" = "25"
+
+ # PL2 override 44W
+ register "tdp_pl2_override" = "44"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 off end # Thermal Subsystem
+ device pci 08.0 off end # Gaussian Mixture Model
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on end # I2C Controller #0
+ device pci 15.1 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""PNP0C50""
+ register "generic.desc" = ""Synaptics Touchpad""
+ register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)"
+ register "generic.probed" = "1"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 0x2c on end
+ end
+ end # I2C Controller #1
+ device pci 15.2 off end # I2C Controller #2
+ device pci 15.3 off end # I2C Controller #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 off end # SATA
+ device pci 19.0 on end # I2C Controller #4
+ device pci 19.1 off end # I2C Controller #5
+ device pci 19.2 off end # UART #2
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 on end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 on end # Serial IO UART0
+ device pci 1f.0 on # LPC
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ chip superio/ite/it8528e
+ device pnp 6e.1 off end
+ device pnp 6e.2 off end
+ device pnp 6e.3 off end
+ device pnp 6e.4 off end
+ device pnp 6e.5 off end
+ device pnp 6e.6 off end
+ device pnp 6e.a off end
+ device pnp 6e.f off end
+ device pnp 6e.10 off end
+ device pnp 6e.11 off end
+ device pnp 6e.12 off end
+ device pnp 6e.13 off end
+ device pnp 6e.14 off end
+ device pnp 6e.17 off end
+ device pnp 6e.18 off end
+ device pnp 6e.19 off end
+ end #superio/ite/it8528e
+ end # LPC Bridge
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl
new file mode 100644
index 0000000000..e110067901
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+){
+ //Platform
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ }
+ // Chipset specific sleep states
+ #include <soc/intel/skylake/acpi/sleepstates.asl>
+
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads b/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads
new file mode 100644
index 0000000000..4d55f2cbc8
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads
@@ -0,0 +1,30 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (Internal,
+ DP1,
+ DP2,
+ HDMI1,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h
new file mode 100644
index 0000000000..5bf1bc48df
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Johanna Schander <coreboot@mimoja.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+ /* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0),
+ /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00),
+ /* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00),
+ /* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00),
+ /* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00),
+ /* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0),
+ /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, 0x84000102, 0x0),
+ /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x0),
+ /* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000),
+ /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x40100102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x04000201, 0x0),
+ /* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0),
+ /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0),
+ /* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000),
+ /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x0),
+ /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0),
+ /* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, 0x44000702, 0x0),
+ /* ISH_GP1 */ _PAD_CFG_STRUCT(GPP_A19, 0x44000702, 0x0),
+ /* ISH_GP2 */ _PAD_CFG_STRUCT(GPP_A20, 0x44000702, 0x0),
+ /* ISH_GP3 */ _PAD_CFG_STRUCT(GPP_A21, 0x44000702, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x40100102, 0x0),
+ /* CORE_VID0 */ _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0),
+ /* CORE_VID1 */ _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0),
+ /* VRALERT# */ _PAD_CFG_STRUCT(GPP_B2, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0),
+ /* SRCCLKREQ0# */ _PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0),
+ /* SRCCLKREQ1# */ _PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0),
+ /* SRCCLKREQ2# */ _PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0),
+ /* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0),
+ /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0),
+ /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0),
+ /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x80880102, 0x3000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0),
+ /* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000),
+ /* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000),
+ /* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000),
+ /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0),
+ /* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000),
+ /* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x0),
+ /* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x40900100, 0x1000),
+ /* RESERVED */ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00),
+ /* RESERVED */ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00),
+ /* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x0),
+ /* UART0_TXD */ _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0),
+ /* UART0_RTS# */ _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0),
+ /* UART0_CTS# */ _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0),
+ /* UART1_RXD */ _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0),
+ /* UART1_TXD */ _PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0),
+ /* UART1_RTS# */ _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0),
+ /* UART1_CTS# */ _PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0),
+ /* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0),
+ /* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0),
+ /* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0),
+ /* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0),
+ /* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0),
+ /* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0),
+ /* UART2_RTS# */ _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0),
+ /* UART2_CTS# */ _PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0),
+ /* SPI1_CS# */ _PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0),
+ /* SPI1_CLK */ _PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0),
+ /* SPI1_MISO */ _PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0),
+ /* SPI1_MOSI */ _PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0),
+ /* FLASHTRIG */ _PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0),
+ /* ISH_I2C0_SDA */ _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0),
+ /* ISH_I2C0_SCL */ _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0),
+ /* ISH_I2C1_SDA */ _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0),
+ /* ISH_I2C1_SCL */ _PAD_CFG_STRUCT(GPP_D8, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x40000100, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x40000100, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x40000100, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x40000100, 0x0),
+ /* ISH_UART0_RXD */ _PAD_CFG_STRUCT(GPP_D13, 0x44000700, 0x0),
+ /* ISH_UART0_TXD */ _PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x0),
+ /* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0),
+ /* ISH_UART0_CTS# */ _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0),
+ /* DMIC_CLK1 */ _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0),
+ /* DMIC_DATA1 */ _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0),
+ /* DMIC_CLK0 */ _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0),
+ /* DMIC_DATA0 */ _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0),
+ /* SPI1_IO2 */ _PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0),
+ /* SPI1_IO3 */ _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0),
+ /* I2S_MCLK */ _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E0, 0x42880100, 0x0),
+ /* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0),
+ /* SATAXPCIE2 */ _PAD_CFG_STRUCT(GPP_E2, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0),
+ /* SATA_DEVSLP0 */ _PAD_CFG_STRUCT(GPP_E4, 0x04000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x82880102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x80180102, 0x0),
+ /* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E11, 0x44000201, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0),
+ /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, 0x44000702, 0x0),
+ /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0),
+ /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0),
+ /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0),
+ /* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000),
+ /* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0),
+ /* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, 0x40900100, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_E23, 0x84000200, 0x1000),
+ /* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0),
+ /* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0),
+ /* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0),
+ /* I2S2_RXD */ _PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0),
+ /* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x2000000),
+ /* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000),
+ /* I2C3_SDA */ _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000),
+ /* I2C3_SCL */ _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000),
+ /* I2C4_SDA */ _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000),
+ /* I2C4_SCL */ _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000),
+ /* ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000),
+ /* ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000),
+ /* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F13, 0x44000102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000102, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F15, 0x44000100, 0x0),
+ /* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0),
+ /* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0),
+ /* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0),
+ /* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0),
+ /* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0),
+ /* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0),
+ /* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0),
+ /* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0),
+ /* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0),
+ /* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0),
+ /* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0),
+ /* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0),
+ /* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x0),
+ /* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0),
+ /* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x0),
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/razer/blade_stealth_kbl/hda_verb.c b/src/mainboard/razer/blade_stealth_kbl/hda_verb.c
new file mode 100644
index 0000000000..457d1d9447
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/hda_verb.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ * Copyright (C) 2019 Johanna Schander <coreboot@mimoja.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+
+ /* Realtek, ALC298 */
+ 0x10ec0298, /* Vendor ID */
+ 0x1a586752, /* Subsystem ID */
+ 12, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x1a586752),
+ AZALIA_PIN_CFG(0, 0x12, 0xb7a60140),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x03a11030),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4075a505),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x21, 0x03211020),
+
+ /* Intel, KabylakeHDMI */
+ 0x8086280b, /* Vendor ID */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of entries */
+ AZALIA_SUBVENDOR(2, 0x80860101),
+ AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/razer/blade_stealth_kbl/mainboard.c b/src/mainboard/razer/blade_stealth_kbl/mainboard.c
new file mode 100644
index 0000000000..7f1f11416a
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/mainboard.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Purism SPC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <string.h>
+#include <cbfs.h>
+
+#define MAX_SERIAL_LENGTH 0x100
+
+const char *smbios_mainboard_serial_number(void)
+{
+ static char serial_number[MAX_SERIAL_LENGTH + 1] = {0};
+ struct cbfsf file;
+
+ if (serial_number[0] != 0)
+ return serial_number;
+
+ if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) {
+ struct region_device cbfs_region;
+ size_t ser_len;
+
+ cbfs_file_data(&cbfs_region, &file);
+
+ ser_len = region_device_sz(&cbfs_region);
+ if (ser_len <= MAX_SERIAL_LENGTH) {
+ if (rdev_readat(&cbfs_region, serial_number, 0, ser_len) == ser_len) {
+ serial_number[ser_len] = 0;
+ return serial_number;
+ }
+ }
+ }
+
+ strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, MAX_SERIAL_LENGTH);
+
+ return serial_number;
+}
diff --git a/src/mainboard/razer/blade_stealth_kbl/ramstage.c b/src/mainboard/razer/blade_stealth_kbl/ramstage.c
new file mode 100644
index 0000000000..94f8071340
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/razer/blade_stealth_kbl/romstage.c b/src/mainboard/razer/blade_stealth_kbl/romstage.c
new file mode 100644
index 0000000000..893d28a2ab
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/romstage.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2017 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <arch/io.h>
+#include "spd/spd.h"
+#include <ec/acpi/ec.h>
+#include <stdint.h>
+#include <stddef.h>
+
+#define SPD_4X_2GB 0
+#define SPD_4X_4GB 1
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ mem_cfg = &mupd->FspmConfig;
+
+
+#if CONFIG(BOARD_RAZER_BLADE_STEALTH_KBL_16GB)
+ u8 spd_index = SPD_4X_4GB;
+#else
+ u8 spd_index = SPD_4X_2GB;
+#endif
+
+ printk(BIOS_INFO, "SPD index %d\n", spd_index);
+
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ struct region_device spd_rdev;
+
+ mem_cfg->DqPinsInterleaved = 0;
+ if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
+ die("spd.bin not found\n");
+ mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
+ /* Memory leak is ok since we have memory mapped boot media */
+ // TODO evaluate google/eve way of loading
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
+ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+
+ mupd->FspmTestConfig.DmiVc1 = 1;
+}
diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc b/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc
new file mode 100644
index 0000000000..3188dbf80e
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Johanna Schander <coreboot@mimoja.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd_util.c
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0000 8GB
+SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b0001 16GB
diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex b/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex
new file mode 100644
index 0000000000..8e6030b635
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 00 05
+78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
+00 B1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2C 00 00 00 00 00 00 00 2B 1F
+4D 54 35 32 4C 31 47 33 32 44 34 50 47 2D 31 30
+37 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex b/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex
new file mode 100644
index 0000000000..fb90339528
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 00 05
+78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
+00 A1 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2C 00 00 00 00 00 00 00 3A 64
+4D 54 35 32 4C 35 31 32 4D 33 32 44 32 50 46 2D
+31 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/spd.h b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h
new file mode 100644
index 0000000000..233d368567
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2019 Johanna Schander <coreboot@mimoja.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#include <gpio.h>
+#include "../gpio.h"
+
+#define RCOMP_TARGET_PARAMS 0x5
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr);
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
+#endif
diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c b/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c
new file mode 100644
index 0000000000..a6f31f0930
--- /dev/null
+++ b/src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include "spd.h"
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ {0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00},
+ {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}};
+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
+{
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {{0, 1, 3, 2, 4, 5, 6, 7}, {1, 0, 4, 5, 2, 3, 6, 7}};
+ memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
+}
+
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = {200, 81, 162};
+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ /* Rcomp target */
+ static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {100, 40, 40, 23, 40};
+
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}