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-rw-r--r--src/northbridge/intel/i945/acpi.c35
-rw-r--r--src/northbridge/intel/i945/i945.h2
-rw-r--r--src/northbridge/intel/i945/northbridge.c2
3 files changed, 7 insertions, 32 deletions
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index 75a6da5175..232575f586 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -3,46 +3,19 @@
#include <types.h>
#include <acpi/acpi.h>
#include <acpi/acpigen.h>
+#include <commonlib/helpers.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include "i945.h"
unsigned long acpi_fill_mcfg(unsigned long current)
{
- struct device *dev;
- u32 pciexbar = 0;
- u32 pciexbar_reg;
- int max_buses;
+ u32 length, pciexbar;
- dev = pcidev_on_root(0, 0);
- if (!dev)
+ if (!decode_pcie_bar(&pciexbar, &length))
return current;
- pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
-
- // MMCFG not supported or not enabled.
- if (!(pciexbar_reg & (1 << 0)))
- return current;
-
- switch ((pciexbar_reg >> 1) & 3) {
- case 0: // 256MB
- pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
- max_buses = 256;
- break;
- case 1: // 128M
- pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
- max_buses = 128;
- break;
- case 2: // 64M
- pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
- max_buses = 64;
- break;
- default: // RSVD
- return current;
- }
-
- if (!pciexbar)
- return current;
+ const int max_buses = length / MiB;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
pciexbar, 0x0, 0x0, max_buses - 1);
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 5275d1bfb7..64a945dca4 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -364,6 +364,8 @@ void sdram_dump_mchbar_registers(void);
u32 decode_igd_memory_size(u32 gms);
u32 decode_tseg_size(const u8 esmramc);
+int decode_pcie_bar(u32 *const base, u32 *const len);
+
/* Romstage mainboard callbacks */
/* Optional: Override the default LPC config. */
void mainboard_lpc_decode(void);
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 20c911620c..103b40f831 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -12,7 +12,7 @@
#include <cpu/intel/smm_reloc.h>
#include "i945.h"
-static int decode_pcie_bar(u32 *const base, u32 *const len)
+int decode_pcie_bar(u32 *const base, u32 *const len)
{
*base = 0;
*len = 0;