diff options
| -rw-r--r-- | src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h | 79 |
1 files changed, 38 insertions, 41 deletions
diff --git a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h index 43b207e4d5..b66d7735d1 100644 --- a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h +++ b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h @@ -39,51 +39,48 @@ static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = { { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ }; +#define CFG_UPD_PORT(port, hide) \ + { \ + .PortIndex = port, \ + .HidePort = hide, \ + .DeEmphasis = 0x00, \ + .PortLinkSpeed = PcieAuto, \ + .MaxPayload = 0x00, \ + .DfxDnTxPreset = 0xFF, \ + .DfxRxPreset = 0xFF, \ + .DfxUpTxPreset = 0xFF, \ + .Sris = 0x00, \ + .PcieCommonClock = 0x00, \ + .NtbPpd = NTB_PORT_TRANSPARENT, \ + .NtbSplitBar = 0x00, \ + .NtbBarSizePBar23 = 0x16, \ + .NtbBarSizePBar4 = 0x16, \ + .NtbBarSizePBar5 = 0x16, \ + .NtbBarSizePBar45 = 0x16, \ + .NtbBarSizeSBar23 = 0x16, \ + .NtbBarSizeSBar4 = 0x16, \ + .NtbBarSizeSBar5 = 0x16, \ + .NtbBarSizeSBar45 = 0x16, \ + .NtbSBar01Prefetch = 0x00, \ + .NtbXlinkCtlOverride = 0x03, \ + } + /* * Standard Tioga Pass Iio PCIe Port Table */ static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = { - // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | - // DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd | - // NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | - // NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | - // NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride - { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, + CFG_UPD_PORT(PORT_1A, NOT_HIDE), + CFG_UPD_PORT(PORT_1B, HIDE), + CFG_UPD_PORT(PORT_1C, HIDE), + CFG_UPD_PORT(PORT_1D, HIDE), + CFG_UPD_PORT(PORT_2A, NOT_HIDE), + CFG_UPD_PORT(PORT_2B, HIDE), + CFG_UPD_PORT(PORT_2C, HIDE), + CFG_UPD_PORT(PORT_2D, HIDE), + CFG_UPD_PORT(PORT_3A, NOT_HIDE), + CFG_UPD_PORT(PORT_3B, HIDE), + CFG_UPD_PORT(PORT_3C, NOT_HIDE), + CFG_UPD_PORT(PORT_3D, HIDE), }; /* |