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-rw-r--r--src/soc/intel/skylake/bootblock/cpu.c18
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c22
2 files changed, 23 insertions, 17 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index 6fc4d92662..d713974358 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -74,25 +74,9 @@ static void bootblock_mdelay(int ms)
static void set_pch_cpu_strap(u8 flex_ratio)
{
- device_t dev = PCH_DEV_SPI;
uint8_t *spibar = (void *)SPI_BASE_ADDRESS;
u32 ssl, ssms, soft_reset_data;
- u8 pcireg;
-
- /* Assign Resources to SPI Controller */
- /* Clear BIT 1-2 SPI Command Register */
- pcireg = pci_read_config8(dev, PCI_COMMAND);
- pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- pci_write_config8(dev, PCI_COMMAND, pcireg);
-
- /* Program Temporary BAR for SPI */
- pci_write_config32(dev, PCI_BASE_ADDRESS_0,
- SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY);
-
- /* Enable Bus Master and MMIO Space */
- pcireg = pci_read_config8(dev, PCI_COMMAND);
- pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config8(dev, PCI_COMMAND, pcireg);
+
/* Set Strap Lock Disable */
ssl = read32(spibar + SPIBAR_RESET_LOCK);
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 1bde80254e..94ed844d3b 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -30,7 +30,29 @@ static void enable_spi_prefetch(void)
pci_write_config8(PCH_DEV_SPI, 0xdc, reg8);
}
+static void enable_spibar(void)
+{
+ device_t dev = PCH_DEV_SPI;
+ u8 pcireg;
+
+ /* Assign Resources to SPI Controller */
+ /* Clear BIT 1-2 SPI Command Register */
+ pcireg = pci_read_config8(dev, PCI_COMMAND);
+ pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_write_config8(dev, PCI_COMMAND, pcireg);
+
+ /* Program Temporary BAR for SPI */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0,
+ SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY);
+
+ /* Enable Bus Master and MMIO Space */
+ pcireg = pci_read_config8(dev, PCI_COMMAND);
+ pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config8(dev, PCI_COMMAND, pcireg);
+}
+
static void bootblock_southbridge_init(void)
{
+ enable_spibar();
enable_spi_prefetch();
}