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-rw-r--r--src/mainboard/google/asurada/Kconfig4
-rw-r--r--src/mainboard/google/asurada/bootblock.c3
2 files changed, 5 insertions, 2 deletions
diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig
index 894d5666b5..7c93815ae8 100644
--- a/src/mainboard/google/asurada/Kconfig
+++ b/src/mainboard/google/asurada/Kconfig
@@ -39,7 +39,7 @@ config MAINBOARD_PART_NUMBER
config DRIVER_TPM_SPI_BUS
hex
- default 0x0
+ default 0x5
# On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus.
# The number here should be a virtual value as (SPI_BUS_NUMBER + 1).
@@ -49,6 +49,6 @@ config BOOT_DEVICE_SPI_FLASH_BUS
config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
- default 0x2
+ default 0x1
endif
diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c
index 5dcae8c79b..cce14381f6 100644
--- a/src/mainboard/google/asurada/bootblock.c
+++ b/src/mainboard/google/asurada/bootblock.c
@@ -1,7 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
+#include <soc/spi.h>
void bootblock_mainboard_init(void)
{
+ mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
+ mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
}