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-rw-r--r--src/northbridge/intel/haswell/raminit.c8
-rw-r--r--src/northbridge/intel/haswell/registers/mchbar.h4
2 files changed, 5 insertions, 7 deletions
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index aaeaadf9ae..7fd6b3f83e 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -65,8 +65,8 @@ static void report_memory_config(void)
int i;
addr_decoder_common = MCHBAR32(MAD_CHNL);
- addr_decode_chan[0] = MCHBAR32(MAD_DIMM_CH0);
- addr_decode_chan[1] = MCHBAR32(MAD_DIMM_CH1);
+ addr_decode_chan[0] = MCHBAR32(MAD_DIMM(0));
+ addr_decode_chan[1] = MCHBAR32(MAD_DIMM(1));
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
(MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
@@ -227,8 +227,8 @@ void setup_sdram_meminfo(struct pei_data *pei_data)
memset(mem_info, 0, sizeof(struct memory_info));
- addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0);
- addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
+ addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0));
+ addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1));
ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index d6e59abe02..60e16e0b98 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -5,9 +5,7 @@
/* Register definitions */
#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */
-#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */
-#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */
-#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on HSW) */
+#define MAD_DIMM(ch) (0x5004 + (ch) * 4)
#define MC_INIT_STATE_G 0x5030
#define MRC_REVISION 0x5034 /* MRC Revision */