summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/northbridge/intel/haswell/finalize.c1
-rw-r--r--src/northbridge/intel/haswell/registers/mchbar.h2
2 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c
index ca10146584..efbaf68074 100644
--- a/src/northbridge/intel/haswell/finalize.c
+++ b/src/northbridge/intel/haswell/finalize.c
@@ -18,6 +18,7 @@ void intel_northbridge_haswell_finalize_smm(void)
pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */
+ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */
MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */
MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
MCHBAR32_OR(REQLIM, 1UL << 31);
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 96d08bfc22..bd99cee585 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -24,6 +24,8 @@
/* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */
#define MMIO_PAVP_MSG 0x5500
+#define PCU_DDR_PTM_CTL 0x5880
+
/* Some power MSRs are also represented in MCHBAR */
#define MCH_PKG_POWER_LIMIT_LO 0x59a0
#define MCH_PKG_POWER_LIMIT_HI 0x59a4