diff options
| -rw-r--r-- | src/mainboard/msi/ms9185/romstage.c | 158 |
1 files changed, 79 insertions, 79 deletions
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 16eb36f8ec..6f5ff3202c 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -50,14 +50,14 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 - unsigned device = (ctrl->channel0[0]) >> 8; - smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); + unsigned device = (ctrl->channel0[0]) >> 8; + smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); + smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); } static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/f.h> @@ -77,131 +77,131 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { - //first node - RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, - RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, - //second node - RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, - RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, - }; + static const uint16_t spd_addr[] = { + //first node + RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, + RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, + //second node + RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, + RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, + }; struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); bcm5785_enable_lpc(); //enable RTC pc87417_enable_dev(RTC_DEV); - } + } - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - setup_ms9185_resource_map(); + setup_ms9185_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif - printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - setup_coherent_ht_domain(); + setup_coherent_ht_domain(); - wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_other_cores(); //bx_a010- wait_all_other_cores_started(bsp_apicid); #endif - /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - bcm5785_early_setup(); + bcm5785_early_setup(); #if 0 - //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); + //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif #if CONFIG_SET_FIDVID - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } #endif #if 1 - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); - } + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset(); + } #endif - allow_all_aps_stop(bsp_apicid); + allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + //It's the time to set ctrl in sysinfo now; + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - enable_smbus(); + enable_smbus(); #if 0 - int i; - for(i = 0; i < 2; i++) { - activate_spd_rom(sysinfo->ctrl+i); - dump_smbus_registers(); - } + int i; + for(i = 0; i < 2; i++) { + activate_spd_rom(sysinfo->ctrl+i); + dump_smbus_registers(); + } #endif - //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ + //do we need apci timer, tsc...., only debug need it for better output + /* all ap stopped? */ // init_timer(); // Need to use TMICT to synchronize FID/VID - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 - print_pci_devices(); + print_pci_devices(); #endif #if 0 // dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); - dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); + dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif - post_cache_as_ram(); + post_cache_as_ram(); } |