diff options
| -rw-r--r-- | src/soc/qualcomm/sc7180/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/uart_bitbang.c | 52 |
3 files changed, 58 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index 2cd1d6355b..70737e9379 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -11,6 +11,8 @@ config SOC_QUALCOMM_SC7180 select HAVE_MONOTONIC_TIMER select ARM64_USE_ARCH_TIMER select SOC_QUALCOMM_COMMON + select HAVE_UART_SPECIAL + select BOOTBLOCK_CONSOLE if SOC_QUALCOMM_SC7180 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 8b65dddf1e..bd2a134216 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -7,11 +7,13 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += spi.c bootblock-y += gpio.c +bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ verstage-y += timer.c verstage-y += spi.c verstage-y += gpio.c +verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ romstage-y += cbmem.c @@ -22,6 +24,7 @@ romstage-y += ../common/mmu.c romstage-y += mmu.c romstage-y += spi.c romstage-y += gpio.c +romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ ramstage-y += soc.c @@ -29,6 +32,7 @@ ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += spi.c ramstage-y += gpio.c +ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c new file mode 100644 index 0000000000..fa0eac8fa7 --- /dev/null +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * Copyright 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> +#include <gpio.h> +#include <types.h> +#include <boot/coreboot_tables.h> + +#define UART_TX_PIN GPIO(44) + +void uart_fill_lb(void *data) +{ + +} + +static void set_tx(int line_state) +{ + gpio_set(UART_TX_PIN, line_state); +} + +void uart_init(int idx) +{ + gpio_output(UART_TX_PIN, 1); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + uart_bitbang_tx_byte(data, set_tx); +} + +void uart_tx_flush(int idx) +{ + /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ +} + +unsigned char uart_rx_byte(int idx) +{ + return 0; /* not implemented */ +} |