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-rw-r--r--src/soc/mediatek/mt8192/Makefile.inc1
-rw-r--r--src/soc/mediatek/mt8192/include/soc/addressmap.h2
-rw-r--r--src/soc/mediatek/mt8192/include/soc/dsi.h55
3 files changed, 58 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 8394c12fba..157ada4dc6 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -39,6 +39,7 @@ romstage-y += mt6359p.c
ramstage-y += ../common/auxadc.c
ramstage-y += dpm.c
+ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
ramstage-y += flash_controller.c
ramstage-y += ../common/gpio.c gpio.c
ramstage-y += ../common/i2c.c i2c.c
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index 0d756b8b7a..6cee8f3897 100644
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -53,12 +53,14 @@ enum {
IOCFG_BR_BASE = IO_PHYS + 0x01D40000,
IOCFG_LM_BASE = IO_PHYS + 0x01E20000,
SSUSB_SIF_BASE = IO_PHYS + 0x01E40300,
+ MIPITX_BASE = IO_PHYS + 0x01E50000,
IOCFG_LB_BASE = IO_PHYS + 0x01E70000,
IOCFG_RT_BASE = IO_PHYS + 0x01EA0000,
IOCFG_LT_BASE = IO_PHYS + 0x01F20000,
IOCFG_TL_BASE = IO_PHYS + 0x01F30000,
MSDC0_TOP_BASE = IO_PHYS + 0x01F50000,
MSDC0_BASE = IO_PHYS + 0x01F60000,
+ DSI0_BASE = IO_PHYS + 0x04010000,
};
#endif
diff --git a/src/soc/mediatek/mt8192/include/soc/dsi.h b/src/soc/mediatek/mt8192/include/soc/dsi.h
new file mode 100644
index 0000000000..ed3d0d8939
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/dsi.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8192_DSI_H
+#define SOC_MEDIATEK_MT8192_DSI_H
+
+#include <soc/dsi_common.h>
+
+/* DSI features */
+#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
+#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
+#define MTK_DSI_DATA_RATE_MIN_MHZ 125
+#define MTK_DSI_HAVE_SIZE_CON 1
+#define PIXEL_STREAM_CUSTOM_HEADER 0xb
+
+/* MIPITX is SOC specific and cannot live in common. */
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+ u32 reserved0[3];
+ u32 lane_con;
+ u32 reserved1[6];
+ u32 pll_pwr;
+ u32 pll_con0;
+ u32 pll_con1;
+ u32 pll_con2;
+ u32 pll_con3;
+ u32 pll_con4;
+ u32 reserved2[65];
+ u32 d2_sw_ctl_en;
+ u32 reserved3[63];
+ u32 d0_sw_ctl_en;
+ u32 reserved4[56];
+ u32 ck_ckmode_en;
+ u32 reserved5[6];
+ u32 ck_sw_ctl_en;
+ u32 reserved6[63];
+ u32 d1_sw_ctl_en;
+ u32 reserved7[63];
+ u32 d3_sw_ctl_en;
+};
+
+check_member(mipi_tx_regs, pll_con4, 0x3c);
+check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
+static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
+
+/* Register values */
+#define DSI_CK_CKMODE_EN BIT(0)
+#define DSI_SW_CTL_EN BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
+
+#define RG_DSI_PLL_EN BIT(4)
+#define RG_DSI_PLL_POSDIV (0x7 << 8)
+
+#endif