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-rw-r--r--src/cpu/samsung/exynos5420/dp.h2
-rw-r--r--src/cpu/samsung/exynos5420/dp_lowlevel.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/samsung/exynos5420/dp.h b/src/cpu/samsung/exynos5420/dp.h
index d260c88af1..4d9d26b859 100644
--- a/src/cpu/samsung/exynos5420/dp.h
+++ b/src/cpu/samsung/exynos5420/dp.h
@@ -1187,7 +1187,7 @@ static inline u32 exynos_fimd_get_base_offset(void)
#define EXYNOS_DP_CLK_ENABLE (1 << 1)
#define EXYNOS_MIE_CLK_ENABLE (3 << 0)
-#define DP_TIMEOUT_LOOP_COUNT 100
+#define DP_TIMEOUT_LOOP_COUNT 1000
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 4
diff --git a/src/cpu/samsung/exynos5420/dp_lowlevel.c b/src/cpu/samsung/exynos5420/dp_lowlevel.c
index 64a296258d..16b9a7ffb2 100644
--- a/src/cpu/samsung/exynos5420/dp_lowlevel.c
+++ b/src/cpu/samsung/exynos5420/dp_lowlevel.c
@@ -452,7 +452,7 @@ unsigned int exynos_dp_detect_hpd(void)
while (exynos_dp_get_plug_in_status() != 0) {
if (timeout_loop == 0)
return -1;
- mdelay(10);
+ mdelay(1);
timeout_loop--;
}
@@ -865,7 +865,7 @@ void exynos_dp_reset_macro(void)
lwrite32(reg, &dp_regs->phy_test);
/* 10 us is the minimum Macro reset time. */
- mdelay(1);
+ udelay(50);
reg &= ~MACRO_RST;
lwrite32(reg, &dp_regs->phy_test);