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-rw-r--r--src/mainboard/google/brya/Kconfig1
-rw-r--r--src/mainboard/google/brya/dsdt.asl19
2 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 3c0875719f..e448e18e21 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -1,6 +1,7 @@
config BOARD_GOOGLE_BASEBOARD_BRYA
def_bool n
select BOARD_ROMSIZE_KB_32768
+ select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SOC_INTEL_ALDERLAKE
diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl
index 10d08e26e2..ebb6ec58f0 100644
--- a/src/mainboard/google/brya/dsdt.asl
+++ b/src/mainboard/google/brya/dsdt.asl
@@ -11,4 +11,23 @@ DefinitionBlock(
0x20110725 // OEM revision
)
{
+ /* Some generic macros */
+ #include <soc/intel/common/acpi/platform.asl>
+
+ /* global NVS and variables */
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+ /* CPU */
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/alderlake/acpi/southbridge.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
}