diff options
56 files changed, 133 insertions, 201 deletions
diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 42c9fbb6cd..7816a7c0bc 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -18,6 +18,8 @@ #include <stddef.h> #include <stdint.h> +void mainboard_romstage_entry(void); + /* * Support setting up a stack frame consisting of MTRR information * for use in bootstrapping the caching attributes after cache-as-ram @@ -62,6 +64,20 @@ void postcar_frame_common_mtrrs(struct postcar_frame *pcf); void *postcar_commit_mtrrs(struct postcar_frame *pcf); /* + * fill_postcar_frame() is called after raminit completes and right before + * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() + * to tag memory ranges as cacheable to speed up execution of postcar and + * early ramstage. + */ +void fill_postcar_frame(struct postcar_frame *pcf); + +/* + * prepare_and_run_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. + */ +void prepare_and_run_postcar(struct postcar_frame *pcf); + +/* * Load and run a program that takes control of execution that * tears down CAR and loads ramstage. The postcar_frame object * indicates how to set up the frame. If caching is enabled at diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 816f41e412..4a7d549347 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -132,6 +132,21 @@ void postcar_frame_common_mtrrs(struct postcar_frame *pcf) postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); } +/* prepare_and_run_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +void prepare_and_run_postcar(struct postcar_frame *pcf) +{ + if (postcar_frame_init(pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + fill_postcar_frame(pcf); + + postcar_frame_common_mtrrs(pcf); + + run_postcar_phase(pcf); + /* We do not return here. */ +} + void *postcar_commit_mtrrs(struct postcar_frame *pcf) { /* diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index a0dc743806..ac81b021a8 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -15,7 +15,6 @@ #include <arch/romstage.h> #include <bootblock_common.h> #include <console/console.h> -#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <arch/symbols.h> @@ -29,21 +28,6 @@ static struct postcar_frame early_mtrrs; -/* prepare_and_run_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void prepare_and_run_postcar(struct postcar_frame *pcf) -{ - if (postcar_frame_init(pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - fill_postcar_frame(pcf); - - postcar_frame_common_mtrrs(pcf); - - run_postcar_phase(pcf); - /* We do not return here. */ -} - static void romstage_main(unsigned long bist) { int i; diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index fafe8384b4..8957c99219 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -18,7 +18,6 @@ #include <cbmem.h> #include <console/console.h> #include <commonlib/helpers.h> -#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <fsp/car.h> diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h deleted file mode 100644 index fd5d7f4e85..0000000000 --- a/src/include/cpu/intel/romstage.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _CPU_INTEL_ROMSTAGE_H -#define _CPU_INTEL_ROMSTAGE_H - -#include <arch/romstage.h> - -void mainboard_romstage_entry(void); - -/* fill_postcar_frame() is called after raminit completes and right before - * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() - * to tag memory ranges as cacheable to speed up execution of postcar and - * early ramstage. */ -void fill_postcar_frame(struct postcar_frame *pcf); - -#endif /* _CPU_INTEL_ROMSTAGE_H */ diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index c95eeda358..7f66fc5aea 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -16,7 +16,7 @@ #include <stdint.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <southbridge/intel/i82801dx/i82801dx.h> #include <northbridge/intel/e7505/raminit.h> diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index ad09c5c68e..32a7871ecf 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -19,7 +19,7 @@ #include <cf9_reset.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <northbridge/intel/i945/i945.h> diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 7a2004f141..0228499181 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -18,7 +18,7 @@ #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 91667ded57..3deae7510f 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -16,7 +16,7 @@ */ #include <stdint.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <device/pnp_ops.h> #include <northbridge/intel/haswell/haswell.h> diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index a93c0ed2a9..5b3a30b4f9 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -18,7 +18,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #include <cbmem.h> diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index e77e3dc18d..f933c772d2 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -18,7 +18,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index b51742907e..1d7c928f17 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -18,7 +18,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #include <cbmem.h> diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index cc5b764b01..8fc135d1c8 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -19,7 +19,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index c3275b5fe1..632ef05573 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -24,7 +24,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index 8af04e3cf9..1477d80ea3 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -20,7 +20,7 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/common/winbond.h> #include <northbridge/intel/x4x/iomap.h> diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index f15a187d94..dc589a5918 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -19,7 +19,7 @@ #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/msr.h> #include <northbridge/intel/x4x/iomap.h> diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 16c3b47a30..a22c90c1f1 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -17,7 +17,7 @@ */ #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <device/pci_ops.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 2740aaa058..ff4c99ed4d 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -24,7 +24,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 7a2b38499b..eaf05a2c38 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -21,7 +21,7 @@ #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index c13d4d6419..989a0cb941 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -22,7 +22,7 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> #include <northbridge/intel/x4x/iomap.h> diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index d36971fc39..f2066647d0 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -16,7 +16,7 @@ #include <stdint.h> #include <stdlib.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 3f6d989fd4..3a2d96f3a0 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include "variant.h" diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 847cc5f584..82dbba5dc5 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -18,7 +18,7 @@ #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pnp_def.h> diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 3fd9aab9c7..1a10931431 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -16,7 +16,7 @@ #include <stdint.h> #include <stddef.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 15acffb052..bad2b6d538 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -19,7 +19,7 @@ #include <cpu/x86/lapic.h> #include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index ec3e2bfbe6..74f86221eb 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -18,7 +18,7 @@ #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index db896824cd..8207638a5b 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -20,7 +20,7 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/common/winbond.h> #include <northbridge/intel/x4x/iomap.h> diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 0981fe8989..bbaad83089 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -17,7 +17,7 @@ #include <cf9_reset.h> #include <delay.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pci_ops.h> diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 243e16112e..9e832208b5 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -24,7 +24,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index bbb73dd57c..e4abab5770 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -20,7 +20,7 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <device/pci_ops.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <northbridge/intel/x4x/iomap.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 067528b87b..3a06a8cd93 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -23,7 +23,7 @@ #include <cpu/x86/lapic.h> #include <romstage_handoff.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <ec/acpi/ec.h> #include <timestamp.h> #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 2b8a9badba..5a8ab942bc 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -25,7 +25,7 @@ #include <cpu/x86/lapic.h> #include <arch/acpi.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 8946179c4a..7f12091ced 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -24,7 +24,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index a4d598f93f..66056a794d 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -23,7 +23,7 @@ #include <cpu/x86/lapic.h> #include <romstage_handoff.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <ec/acpi/ec.h> #include <timestamp.h> #include <arch/acpi.h> diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 196f0a510f..30ebf4431d 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -24,7 +24,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 228bcb581e..552ebd2113 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -16,7 +16,7 @@ */ #include <cpu/intel/haswell/haswell.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/pei_data.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 9a63cffeae..11af6e334f 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -18,7 +18,6 @@ #include <arch/romstage.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> #include "e7505.h" diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 4814e356b5..6e2f7037c2 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -22,7 +22,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> -#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <program_loading.h> diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 7c16761bb5..c853a3a1f4 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -21,7 +21,7 @@ #include <device/pci_ops.h> #include <arch/acpi.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <northbridge/intel/gm45/gm45.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index b1d86db51a..5bc74f8703 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -18,10 +18,10 @@ #include <arch/romstage.h> #include <console/console.h> +#include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <cpu/intel/romstage.h> #include <stage_cache.h> #include "haswell.h" diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index 6a1730eea6..6c540a512a 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -20,7 +20,6 @@ #include <cbmem.h> #include <console/console.h> #include <commonlib/helpers.h> -#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> #include "i440bx.h" diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index b0764f67ed..8179f17888 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -21,7 +21,6 @@ #include <cbmem.h> #include "i945.h" #include <console/console.h> -#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <cpu/intel/smm_reloc.h> diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c index 8787df6898..1687ddf78b 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/nehalem/memmap.c @@ -20,7 +20,6 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <stage_cache.h> diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index eaf27f699f..9908f110cd 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -24,7 +24,6 @@ #include <cbmem.h> #include <northbridge/intel/pineview/pineview.h> #include <cpu/x86/mtrr.h> -#include <cpu/intel/romstage.h> #include <cpu/intel/smm_reloc.h> #include <stdint.h> #include <stage_cache.h> diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index e184f789d0..e60738ced5 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -26,7 +26,7 @@ #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <cpu/x86/lapic.h> #include "raminit.h" #include "pineview.h" diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 44bbbd201b..fa29b3782b 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/intel/romstage.h> #include <cpu/intel/smm_reloc.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index bfcf79dd23..1b402dcc56 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -22,7 +22,7 @@ #include <cpu/x86/lapic.h> #include <timestamp.h> #include "sandybridge.h" -#include <cpu/intel/romstage.h> +#include <arch/romstage.h> #include <device/pci_def.h> #include <device/device.h> #include <northbridge/intel/sandybridge/chip.h> diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index b8a3b94a78..2f50768c46 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -24,7 +24,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> -#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <northbridge/intel/x4x/x4x.h> #include <program_loading.h> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1464d2c6b3..2c283396c9 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/romstage.h> #include <device/pci_ops.h> #include <arch/symbols.h> @@ -193,20 +192,15 @@ void set_max_freq(void) cpu_set_p_state_to_turbo_ratio(); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { - struct postcar_frame pcf; - uintptr_t top_of_ram; bool s3wake; + size_t var_size; struct chipset_power_state *ps = pmc_get_power_state(); - uintptr_t smm_base; - size_t smm_size, var_size; const void *new_var_data; timestamp_add_now(TS_START_ROMSTAGE); - console_init(); - soc_early_romstage_init(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; @@ -227,10 +221,14 @@ asmlinkage void car_stage_entry(void) else printk(BIOS_ERR, "Failed to determine variable data\n"); - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - mainboard_save_dimm_info(); +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t smm_base; + size_t smm_size; /* * We need to make sure ramstage will be run cached. At this point exact @@ -240,12 +238,9 @@ asmlinkage void car_stage_entry(void) top_of_ram = (uintptr_t) cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); - /* Cache the memory-mapped boot media. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. @@ -254,9 +249,7 @@ asmlinkage void car_stage_entry(void) * region for other purposes. */ smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); } static void fill_console_params(FSPM_UPD *mupd) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index f20c363a35..aa9fa6b66a 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -54,23 +54,6 @@ static struct postcar_frame early_mtrrs; -static void fill_postcar_frame(struct postcar_frame *pcf); - -/* prepare_and_run_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void prepare_and_run_postcar(struct postcar_frame *pcf) -{ - if (postcar_frame_init(pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - fill_postcar_frame(pcf); - - postcar_frame_common_mtrrs(pcf); - - run_postcar_phase(pcf); - /* We do not return here. */ -} - static void program_base_addresses(void) { uint32_t reg; @@ -260,7 +243,7 @@ void romstage_common(struct romstage_params *params) romstage_handoff_init(prev_sleep_state == ACPI_S3); } -static void fill_postcar_frame(struct postcar_frame *pcf) +void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 3f264ff5ec..b3662e1591 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -21,7 +21,6 @@ #include <bootmode.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <elog.h> #include <program_loading.h> diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 9f02c8b1d3..5711c15142 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/romstage.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> @@ -128,15 +127,11 @@ static void save_dimm_info(void) printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { bool s3wake; - struct postcar_frame pcf; - uintptr_t top_of_ram; struct chipset_power_state *ps = pmc_get_power_state(); - console_init(); - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* initialize Heci interface */ @@ -148,9 +143,11 @@ asmlinkage void car_stage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); +} +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; /* * We need to make sure ramstage will be run cached. At this * point exact location of ramstage in cbmem is not known. @@ -160,10 +157,5 @@ asmlinkage void car_stage_entry(void) top_of_ram = (uintptr_t) cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - run_postcar_phase(&pcf); + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 9c41486aa2..cbd451ae0d 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/romstage.h> #include <arch/io.h> #include <cbmem.h> @@ -137,16 +136,8 @@ static void early_tco_init(void) outw(reg16, tco_base + TCO2_STS); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { - - struct postcar_frame pcf; - uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; - - console_init(); - printk(BIOS_DEBUG, "FSP TempRamInit was successful...\n"); mainboard_config_gpios(); @@ -158,9 +149,13 @@ asmlinkage void car_stage_entry(void) #if CONFIG(DISPLAY_HOBS) display_fsp_smbios_memory_info_hob(); #endif +} - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t smm_base; + size_t smm_size; /* * We need to make sure ramstage will be run cached. At this point exact @@ -168,12 +163,9 @@ asmlinkage void car_stage_entry(void) * 16 megs under cbmem top which is a safe bet to cover ramstage. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); - /* Cache the memory-mapped boot media. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. @@ -181,12 +173,8 @@ asmlinkage void car_stage_entry(void) * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - if (CONFIG(HAVE_SMI_HANDLER)) { - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); - } - - run_postcar_phase(&pcf); + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); } static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 8312f178e4..67ef2bb6ce 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/romstage.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> @@ -112,15 +111,11 @@ static void save_dimm_info(void) printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { bool s3wake; - struct postcar_frame pcf; - uintptr_t top_of_ram; struct chipset_power_state *ps = pmc_get_power_state(); - console_init(); - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* initialize Heci interface */ @@ -132,9 +127,11 @@ asmlinkage void car_stage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); +} +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; /* * We need to make sure ramstage will be run cached. At this * point exact location of ramstage in cbmem is not known. @@ -144,10 +141,5 @@ asmlinkage void car_stage_entry(void) top_of_ram = (uintptr_t) cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - run_postcar_phase(&pcf); + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 0489621045..bd30271d77 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -28,12 +28,11 @@ #include <soc/reg_access.h> #include <soc/storage_test.h> +static struct postcar_frame early_mtrrs; + asmlinkage void car_stage_c_entry(void) { - struct postcar_frame pcf; bool s3wake; - uintptr_t top_of_ram; - uintptr_t top_of_low_usable_memory; post_code(0x20); console_init(); @@ -63,28 +62,33 @@ asmlinkage void car_stage_c_entry(void) /* Initialize the PCIe bridges */ pcie_init(); - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); + prepare_and_run_postcar(&early_mtrrs); + /* We do not return here. */ +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t top_of_low_usable_memory; /* Locate the top of RAM */ top_of_low_usable_memory = (uintptr_t) cbmem_top(); top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); /* Cache postcar and ramstage */ - postcar_frame_add_mtrr(&pcf, top_of_ram - (16 * MiB), 16 * MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB, MTRR_TYPE_WRBACK); /* Cache RMU area */ - postcar_frame_add_mtrr(&pcf, (uintptr_t) top_of_low_usable_memory, + postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory, 0x10000, MTRR_TYPE_WRTHROUGH); /* Cache ESRAM */ - postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); + pcf->skip_common_mtrr = 1; /* Cache SPI flash - Write protect not supported */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH); - - run_postcar_phase(&pcf); + postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH); } static struct chipset_power_state power_state; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8b5cd18195..2412f22a27 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/romstage.h> #include <arch/symbols.h> #include <assert.h> @@ -140,15 +139,11 @@ static void save_dimm_info(void) printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { bool s3wake; - struct postcar_frame pcf; - uintptr_t top_of_ram; struct chipset_power_state *ps; - console_init(); - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); @@ -159,8 +154,13 @@ asmlinkage void car_stage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t smm_base; + size_t smm_size; /* * We need to make sure ramstage will be run cached. At this @@ -171,28 +171,17 @@ asmlinkage void car_stage_entry(void) top_of_ram = (uintptr_t) cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - if (CONFIG(HAVE_SMI_HANDLER)) { - uintptr_t smm_base; - size_t smm_size; + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, - MTRR_TYPE_WRBACK); - } - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - run_postcar_phase(&pcf); + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); } static void cpu_flex_override(FSP_M_CONFIG *m_cfg) |