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-rw-r--r--src/soc/intel/elkhartlake/include/soc/romstage.h22
-rw-r--r--src/soc/intel/elkhartlake/include/soc/soc_chip.h8
-rw-r--r--src/soc/intel/elkhartlake/include/soc/systemagent.h43
-rw-r--r--src/soc/intel/elkhartlake/romstage/Makefile.inc7
-rw-r--r--src/soc/intel/elkhartlake/romstage/fsp_params.c31
-rw-r--r--src/soc/intel/elkhartlake/romstage/pch.c10
-rw-r--r--src/soc/intel/elkhartlake/romstage/romstage.c143
-rw-r--r--src/soc/intel/elkhartlake/romstage/systemagent.c29
8 files changed, 293 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/include/soc/romstage.h b/src/soc/intel/elkhartlake/include/soc/romstage.h
new file mode 100644
index 0000000000..baa35c5216
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/romstage.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <fsp/api.h>
+
+/* Provide a callback to allow mainboard to override the DRAM part number. */
+bool mainboard_get_dram_part_num(const char **part_num, size_t *len);
+void mainboard_memory_init_params(FSPM_UPD *mupd);
+void systemagent_early_init(void);
+void romstage_pch_init(void);
+
+/* Board type */
+enum board_type {
+ BOARD_TYPE_MOBILE = 0,
+ BOARD_TYPE_DESKTOP = 1,
+ BOARD_TYPE_ULT_ULX = 5,
+ BOARD_TYPE_SERVER = 7
+};
+
+#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/elkhartlake/include/soc/soc_chip.h b/src/soc/intel/elkhartlake/include/soc/soc_chip.h
new file mode 100644
index 0000000000..6fccc64b53
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/soc_chip.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ELKHARTLAKE_SOC_CHIP_H_
+#define _SOC_ELKHARTLAKE_SOC_CHIP_H_
+
+#include "../../chip.h"
+
+#endif /* _SOC_ELKHARTLAKE_SOC_CHIP_H_ */
diff --git a/src/soc/intel/elkhartlake/include/soc/systemagent.h b/src/soc/intel/elkhartlake/include/soc/systemagent.h
new file mode 100644
index 0000000000..0abfbfcb07
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/systemagent.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_ELKHARTLAKE_SYSTEMAGENT_H
+#define SOC_ELKHARTLAKE_SYSTEMAGENT_H
+
+#include <intelblocks/systemagent.h>
+
+/* Device 0:0.0 PCI configuration space */
+
+#define EPBAR 0x40
+#define DMIBAR 0x68
+#define CAPID0_A 0xe4
+#define VTD_DISABLE (1 << 23)
+
+#define BIOS_RESET_CPL 0x5da8
+#define GFXVTBAR 0x5400
+#define EDRAMBAR 0x5408
+#define VTVC0BAR 0x5410
+#define REGBAR 0x5420
+#define VTBAR_ENABLED 0x01
+#define VTBAR_MASK 0x7ffffff000ull
+
+#define MCH_PKG_POWER_LIMIT_LO 0x59a0
+#define MCH_PKG_POWER_LIMIT_HI 0x59a4
+#define MCH_DDR_POWER_LIMIT_LO 0x58e0
+#define MCH_DDR_POWER_LIMIT_HI 0x58e4
+
+#define IMRBASE 0x6A40
+#define IMRLIMIT 0x6A48
+
+static const struct sa_mmio_descriptor soc_vtd_resources[] = {
+ { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
+ { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
+};
+
+#define V_P2SB_CFG_IBDF_BUS 0
+#define V_P2SB_CFG_IBDF_DEV 30
+#define V_P2SB_CFG_IBDF_FUNC 7
+#define V_P2SB_CFG_HBDF_BUS 0
+#define V_P2SB_CFG_HBDF_DEV 30
+#define V_P2SB_CFG_HBDF_FUNC 6
+
+#endif
diff --git a/src/soc/intel/elkhartlake/romstage/Makefile.inc b/src/soc/intel/elkhartlake/romstage/Makefile.inc
new file mode 100644
index 0000000000..a1a6c6638d
--- /dev/null
+++ b/src/soc/intel/elkhartlake/romstage/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += fsp_params.c
+romstage-y += ../../../../cpu/intel/car/romstage.c
+romstage-y += romstage.c
+romstage-y += pch.c
+romstage-y += systemagent.c
diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c
new file mode 100644
index 0000000000..3961dfc167
--- /dev/null
+++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <fsp/util.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
+
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
+ const struct soc_intel_elkhartlake_config *config)
+{
+ /* TODO: Update with UPD details as FSP matures */
+}
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+ const struct soc_intel_elkhartlake_config *config = config_of_soc();
+ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+ soc_memory_init_params(m_cfg, config);
+
+ mainboard_memory_init_params(mupd);
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ /* TODO: Update later together with UPD updates */
+}
diff --git a/src/soc/intel/elkhartlake/romstage/pch.c b/src/soc/intel/elkhartlake/romstage/pch.c
new file mode 100644
index 0000000000..d3c2554425
--- /dev/null
+++ b/src/soc/intel/elkhartlake/romstage/pch.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/smbus.h>
+#include <soc/romstage.h>
+
+void romstage_pch_init(void)
+{
+ /* Program SMBUS_BASE_ADDRESS and Enable it */
+ smbus_common_init();
+}
diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c
new file mode 100644
index 0000000000..d68d2dafd5
--- /dev/null
+++ b/src/soc/intel/elkhartlake/romstage/romstage.c
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/romstage.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <intelblocks/cfg.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/pmclib.h>
+#include <memory_info.h>
+#include <soc/intel/common/smbios.h>
+#include <soc/iomap.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
+
+#define FSP_SMBIOS_MEMORY_INFO_GUID \
+{ \
+ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
+ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
+}
+
+bool mainboard_get_dram_part_num(const char **part_num, size_t *len)
+{
+ /* Default implementation, no need to override part number. */
+ return false;
+}
+
+/* Save the DIMM information for SMBIOS table 17 */
+static void save_dimm_info(void)
+{
+ int node, channel, dimm, dimm_max, index;
+ size_t hob_size;
+ const CONTROLLER_INFO *ctrlr_info;
+ const CHANNEL_INFO *channel_info;
+ const DIMM_INFO *src_dimm;
+ struct dimm_info *dest_dimm;
+ struct memory_info *mem_info;
+ const MEMORY_INFO_DATA_HOB *meminfo_hob;
+ const uint8_t smbios_memory_info_guid[16] =
+ FSP_SMBIOS_MEMORY_INFO_GUID;
+ const uint8_t *serial_num;
+ const char *dram_part_num = NULL;
+ size_t dram_part_num_len;
+ bool is_dram_part_overridden = false;
+
+ /* Locate the memory info HOB, presence validated by raminit */
+ meminfo_hob = fsp_find_extension_hob_by_guid(
+ smbios_memory_info_guid,
+ &hob_size);
+ if (meminfo_hob == NULL || hob_size == 0) {
+ printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
+ return;
+ }
+
+ /*
+ * Allocate CBMEM area for DIMM information used to populate SMBIOS
+ * table 17
+ */
+ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+ if (mem_info == NULL) {
+ printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
+ return;
+ }
+ memset(mem_info, 0, sizeof(*mem_info));
+
+ /* Allow mainboard to override DRAM part number. */
+ is_dram_part_overridden = mainboard_get_dram_part_num(&dram_part_num,
+ &dram_part_num_len);
+
+ /* Save available DIMM information */
+ index = 0;
+ dimm_max = ARRAY_SIZE(mem_info->dimm);
+ for (node = 0; node < MAX_NODE; node++) {
+ ctrlr_info = &meminfo_hob->Controller[node];
+ for (channel = 0; channel < MAX_CH && index < dimm_max;
+ channel++) {
+ channel_info = &ctrlr_info->ChannelInfo[channel];
+ if (channel_info->Status != 2)
+ continue;
+
+ for (dimm = 0; dimm < MAX_DIMM && index < dimm_max;
+ dimm++) {
+ src_dimm = &channel_info->DimmInfo[dimm];
+ dest_dimm = &mem_info->dimm[index];
+ if (src_dimm->Status != DIMM_PRESENT)
+ continue;
+
+ /* If there is no DRAM part number overridden by
+ * mainboard then use original one. */
+ if (!is_dram_part_overridden) {
+ dram_part_num_len = sizeof(src_dimm->ModulePartNum);
+ dram_part_num = (const char *)
+ &src_dimm->ModulePartNum[0];
+ }
+
+ u8 memProfNum = meminfo_hob->MemoryProfile;
+ serial_num = src_dimm->SpdSave +
+ SPD_SAVE_OFFSET_SERIAL;
+
+ /* Populate the DIMM information */
+ dimm_info_fill(dest_dimm,
+ src_dimm->DimmCapacity,
+ meminfo_hob->MemoryType,
+ meminfo_hob->ConfiguredMemoryClockSpeed,
+ src_dimm->RankInDimm,
+ channel_info->ChannelId,
+ src_dimm->DimmId,
+ dram_part_num,
+ dram_part_num_len,
+ serial_num,
+ meminfo_hob->DataWidth,
+ meminfo_hob->VddVoltage[memProfNum],
+ meminfo_hob->EccSupport,
+ src_dimm->MfgId,
+ src_dimm->SpdModuleType);
+ index++;
+ }
+ }
+ }
+ mem_info->dimm_cnt = index;
+ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+}
+
+void mainboard_romstage_entry(void)
+{
+ bool s3wake;
+ struct chipset_power_state *ps = pmc_get_power_state();
+
+ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
+ systemagent_early_init();
+ /* Program PCH init */
+ romstage_pch_init();
+ /* initialize Heci interface */
+ heci_init(HECI1_BASE_ADDRESS);
+
+ s3wake = pmc_fill_power_state(ps) == ACPI_S3;
+ fsp_memory_init(s3wake);
+ pmc_set_disb();
+ if (!s3wake)
+ save_dimm_info();
+}
diff --git a/src/soc/intel/elkhartlake/romstage/systemagent.c b/src/soc/intel/elkhartlake/romstage/systemagent.c
new file mode 100644
index 0000000000..6e9b9fa486
--- /dev/null
+++ b/src/soc/intel/elkhartlake/romstage/systemagent.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/romstage.h>
+#include <soc/systemagent.h>
+
+void systemagent_early_init(void)
+{
+ static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
+ { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
+ { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
+ { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
+ };
+
+ static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = {
+ { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
+ { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
+ };
+
+ /* Set Fixed MMIO address into PCI configuration space */
+ sa_set_pci_bar(soc_fixed_pci_resources,
+ ARRAY_SIZE(soc_fixed_pci_resources));
+ /* Set Fixed MMIO address into MCH base address */
+ sa_set_mch_bar(soc_fixed_mch_resources,
+ ARRAY_SIZE(soc_fixed_mch_resources));
+ /* Enable PAM registers */
+ enable_pam_region();
+}