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-rw-r--r--src/mainboard/google/veyron/Kconfig (renamed from src/mainboard/google/veyron_jerry/Kconfig)11
-rw-r--r--src/mainboard/google/veyron/Kconfig.name39
-rw-r--r--src/mainboard/google/veyron/Makefile.inc (renamed from src/mainboard/google/veyron_jerry/Makefile.inc)0
-rw-r--r--src/mainboard/google/veyron/board.h (renamed from src/mainboard/google/veyron_shark/board.h)6
-rw-r--r--src/mainboard/google/veyron/boardid.c (renamed from src/mainboard/google/veyron_jerry/boardid.c)0
-rw-r--r--src/mainboard/google/veyron/bootblock.c (renamed from src/mainboard/google/veyron_jerry/bootblock.c)0
-rw-r--r--src/mainboard/google/veyron/chromeos.c (renamed from src/mainboard/google/veyron_jerry/chromeos.c)0
-rw-r--r--src/mainboard/google/veyron/devicetree.cb (renamed from src/mainboard/google/veyron_jerry/devicetree.cb)0
-rw-r--r--src/mainboard/google/veyron/mainboard.c (renamed from src/mainboard/google/veyron_minnie/mainboard.c)2
-rw-r--r--src/mainboard/google/veyron/memlayout.ld (renamed from src/mainboard/google/veyron_jerry/memlayout.ld)0
-rw-r--r--src/mainboard/google/veyron/reset.c (renamed from src/mainboard/google/veyron_jerry/reset.c)0
-rw-r--r--src/mainboard/google/veyron/romstage.c (renamed from src/mainboard/google/veyron_jerry/romstage.c)0
-rw-r--r--src/mainboard/google/veyron/sdram_configs.c (renamed from src/mainboard/google/veyron_jerry/sdram_configs.c)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-4GB.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-4GB.inc)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-ddr3-nanya-2GB.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-2GB.inc)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-4GB.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-4GB.inc)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-2GB.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-2GB.inc)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-4GB.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-4GB.inc)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-2GB.inc)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-4GB.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-4GB.inc)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-2GB.inc)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-4GB.inc)0
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-unused.inc (renamed from src/mainboard/google/veyron_jerry/sdram_inf/sdram-unused.inc)0
-rw-r--r--src/mainboard/google/veyron_jerry/Kconfig.name2
-rw-r--r--src/mainboard/google/veyron_jerry/board.h31
-rw-r--r--src/mainboard/google/veyron_jerry/mainboard.c167
-rw-r--r--src/mainboard/google/veyron_mighty/Kconfig85
-rw-r--r--src/mainboard/google/veyron_mighty/Kconfig.name2
-rw-r--r--src/mainboard/google/veyron_mighty/Makefile.inc42
-rw-r--r--src/mainboard/google/veyron_mighty/board.h31
-rw-r--r--src/mainboard/google/veyron_mighty/boardid.c49
-rw-r--r--src/mainboard/google/veyron_mighty/bootblock.c78
-rw-r--r--src/mainboard/google/veyron_mighty/chromeos.c148
-rw-r--r--src/mainboard/google/veyron_mighty/devicetree.cb26
-rw-r--r--src/mainboard/google/veyron_mighty/mainboard.c167
-rw-r--r--src/mainboard/google/veyron_mighty/memlayout.ld1
-rw-r--r--src/mainboard/google/veyron_mighty/reset.c30
-rw-r--r--src/mainboard/google/veyron_mighty/romstage.c117
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_configs.c54
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-4GB.inc77
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-4GB.inc77
-rw-r--r--src/mainboard/google/veyron_mighty/sdram_inf/sdram-unused.inc3
-rw-r--r--src/mainboard/google/veyron_minnie/Kconfig85
-rw-r--r--src/mainboard/google/veyron_minnie/Kconfig.name2
-rw-r--r--src/mainboard/google/veyron_minnie/Makefile.inc42
-rw-r--r--src/mainboard/google/veyron_minnie/board.h31
-rw-r--r--src/mainboard/google/veyron_minnie/board_info.txt1
-rw-r--r--src/mainboard/google/veyron_minnie/boardid.c49
-rw-r--r--src/mainboard/google/veyron_minnie/bootblock.c78
-rw-r--r--src/mainboard/google/veyron_minnie/chromeos.c148
-rw-r--r--src/mainboard/google/veyron_minnie/devicetree.cb26
-rw-r--r--src/mainboard/google/veyron_minnie/memlayout.ld1
-rw-r--r--src/mainboard/google/veyron_minnie/reset.c30
-rw-r--r--src/mainboard/google/veyron_minnie/romstage.c118
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_configs.c54
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-4GB.inc77
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-4GB.inc77
-rw-r--r--src/mainboard/google/veyron_minnie/sdram_inf/sdram-unused.inc3
-rw-r--r--src/mainboard/google/veyron_pinky/Kconfig85
-rw-r--r--src/mainboard/google/veyron_pinky/Kconfig.name2
-rw-r--r--src/mainboard/google/veyron_pinky/Makefile.inc42
-rw-r--r--src/mainboard/google/veyron_pinky/board.h31
-rw-r--r--src/mainboard/google/veyron_pinky/boardid.c49
-rw-r--r--src/mainboard/google/veyron_pinky/bootblock.c78
-rw-r--r--src/mainboard/google/veyron_pinky/chromeos.c149
-rw-r--r--src/mainboard/google/veyron_pinky/devicetree.cb26
-rw-r--r--src/mainboard/google/veyron_pinky/mainboard.c213
-rw-r--r--src/mainboard/google/veyron_pinky/memlayout.ld1
-rw-r--r--src/mainboard/google/veyron_pinky/reset.c30
-rw-r--r--src/mainboard/google/veyron_pinky/romstage.c125
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_configs.c54
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-4GB.inc77
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-4GB.inc77
-rw-r--r--src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc3
-rw-r--r--src/mainboard/google/veyron_shark/Kconfig85
-rw-r--r--src/mainboard/google/veyron_shark/Kconfig.name2
-rw-r--r--src/mainboard/google/veyron_shark/Makefile.inc42
-rw-r--r--src/mainboard/google/veyron_shark/boardid.c49
-rw-r--r--src/mainboard/google/veyron_shark/bootblock.c78
-rw-r--r--src/mainboard/google/veyron_shark/chromeos.c148
-rw-r--r--src/mainboard/google/veyron_shark/devicetree.cb26
-rw-r--r--src/mainboard/google/veyron_shark/mainboard.c157
-rw-r--r--src/mainboard/google/veyron_shark/memlayout.ld1
-rw-r--r--src/mainboard/google/veyron_shark/reset.c30
-rw-r--r--src/mainboard/google/veyron_shark/romstage.c118
-rw-r--r--src/mainboard/google/veyron_shark/sdram_configs.c54
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-4GB.inc77
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-4GB.inc77
-rw-r--r--src/mainboard/google/veyron_shark/sdram_inf/sdram-unused.inc3
-rw-r--r--src/mainboard/google/veyron_speedy/Kconfig85
-rw-r--r--src/mainboard/google/veyron_speedy/Kconfig.name2
-rw-r--r--src/mainboard/google/veyron_speedy/Makefile.inc42
-rw-r--r--src/mainboard/google/veyron_speedy/board.h31
-rw-r--r--src/mainboard/google/veyron_speedy/boardid.c49
-rw-r--r--src/mainboard/google/veyron_speedy/bootblock.c78
-rw-r--r--src/mainboard/google/veyron_speedy/chromeos.c148
-rw-r--r--src/mainboard/google/veyron_speedy/devicetree.cb26
-rw-r--r--src/mainboard/google/veyron_speedy/mainboard.c167
-rw-r--r--src/mainboard/google/veyron_speedy/memlayout.ld1
-rw-r--r--src/mainboard/google/veyron_speedy/reset.c30
-rw-r--r--src/mainboard/google/veyron_speedy/romstage.c118
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_configs.c54
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-4GB.inc78
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc77
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc78
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc77
-rw-r--r--src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc3
152 files changed, 50 insertions, 8504 deletions
diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron/Kconfig
index 1bbcf9445a..c474bd652f 100644
--- a/src/mainboard/google/veyron_jerry/Kconfig
+++ b/src/mainboard/google/veyron/Kconfig
@@ -17,7 +17,10 @@
## Foundation, Inc.
##
-if BOARD_GOOGLE_VEYRON_JERRY
+config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards
+ def_bool n
+
+if BOARD_GOOGLE_VEYRON
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -43,11 +46,11 @@ config CHROMEOS
config MAINBOARD_DIR
string
- default google/veyron_jerry
+ default google/veyron
config MAINBOARD_PART_NUMBER
string
- default "Veyron_Jerry"
+ default "Veyron"
config MAINBOARD_VENDOR
string
@@ -82,4 +85,4 @@ config PMIC_BUS
int
default 0
-endif # BOARD_GOOGLE_VEYRON_JERRY
+endif # BOARD_GOOGLE_VEYRON
diff --git a/src/mainboard/google/veyron/Kconfig.name b/src/mainboard/google/veyron/Kconfig.name
new file mode 100644
index 0000000000..5c7a44b8c4
--- /dev/null
+++ b/src/mainboard/google/veyron/Kconfig.name
@@ -0,0 +1,39 @@
+config BOARD_GOOGLE_VEYRON_GUS
+ bool "Veyron_Gus"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_JAQ
+ bool "Veyron_Jaq"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_JERRY
+ bool "Veyron_Jerry"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_MIGHTY
+ bool "Veyron_Mighty"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_MINNIE
+ bool "Veyron_Minnie"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_NICKY
+ bool "Veyron_Nicky"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_PINKY
+ bool "Veyron_Pinky"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_SHARK
+ bool "Veyron_Shark"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_SPEEDY
+ bool "Veyron_Speedy"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_THEA
+ bool "Veyron_Thea"
+ select BOARD_GOOGLE_VEYRON
diff --git a/src/mainboard/google/veyron_jerry/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc
index ea1c6063e7..ea1c6063e7 100644
--- a/src/mainboard/google/veyron_jerry/Makefile.inc
+++ b/src/mainboard/google/veyron/Makefile.inc
diff --git a/src/mainboard/google/veyron_shark/board.h b/src/mainboard/google/veyron/board.h
index 47bbbdf9ae..a200e1634f 100644
--- a/src/mainboard/google/veyron_shark/board.h
+++ b/src/mainboard/google/veyron/board.h
@@ -17,8 +17,8 @@
* Foundation, Inc.
*/
-#ifndef __MAINBOARD_GOOGLE_VEYRON_SHARK_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_SHARK_BOARD_H
+#ifndef __MAINBOARD_GOOGLE_VEYRON_BOARD_H
+#define __MAINBOARD_GOOGLE_VEYRON_BOARD_H
#include <boardid.h>
#include <gpio.h>
@@ -28,4 +28,4 @@
void setup_chromeos_gpios(void);
-#endif /* __MAINBOARD_GOOGLE_VEYRON_SHARK_BOARD_H */
+#endif /* __MAINBOARD_GOOGLE_VEYRON_BOARD_H */
diff --git a/src/mainboard/google/veyron_jerry/boardid.c b/src/mainboard/google/veyron/boardid.c
index f7cddcc4fe..f7cddcc4fe 100644
--- a/src/mainboard/google/veyron_jerry/boardid.c
+++ b/src/mainboard/google/veyron/boardid.c
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron/bootblock.c
index ae74972340..ae74972340 100644
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ b/src/mainboard/google/veyron/bootblock.c
diff --git a/src/mainboard/google/veyron_jerry/chromeos.c b/src/mainboard/google/veyron/chromeos.c
index 54896391a8..54896391a8 100644
--- a/src/mainboard/google/veyron_jerry/chromeos.c
+++ b/src/mainboard/google/veyron/chromeos.c
diff --git a/src/mainboard/google/veyron_jerry/devicetree.cb b/src/mainboard/google/veyron/devicetree.cb
index b958e267d4..b958e267d4 100644
--- a/src/mainboard/google/veyron_jerry/devicetree.cb
+++ b/src/mainboard/google/veyron/devicetree.cb
diff --git a/src/mainboard/google/veyron_minnie/mainboard.c b/src/mainboard/google/veyron/mainboard.c
index 0de89af99b..b8f9aae116 100644
--- a/src/mainboard/google/veyron_minnie/mainboard.c
+++ b/src/mainboard/google/veyron/mainboard.c
@@ -141,7 +141,7 @@ void lb_board(struct lb_header *header)
void mainboard_power_on_backlight(void)
{
gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(20);
+ mdelay(120);
gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
mdelay(10);
gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
diff --git a/src/mainboard/google/veyron_jerry/memlayout.ld b/src/mainboard/google/veyron/memlayout.ld
index ead7f47838..ead7f47838 100644
--- a/src/mainboard/google/veyron_jerry/memlayout.ld
+++ b/src/mainboard/google/veyron/memlayout.ld
diff --git a/src/mainboard/google/veyron_jerry/reset.c b/src/mainboard/google/veyron/reset.c
index bc26ece4b3..bc26ece4b3 100644
--- a/src/mainboard/google/veyron_jerry/reset.c
+++ b/src/mainboard/google/veyron/reset.c
diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron/romstage.c
index 5ccbe3ec23..5ccbe3ec23 100644
--- a/src/mainboard/google/veyron_jerry/romstage.c
+++ b/src/mainboard/google/veyron/romstage.c
diff --git a/src/mainboard/google/veyron_jerry/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c
index 023eb3772c..023eb3772c 100644
--- a/src/mainboard/google/veyron_jerry/sdram_configs.c
+++ b/src/mainboard/google/veyron/sdram_configs.c
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
index 5b784cdcb7..5b784cdcb7 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-4GB.inc
index 9f2ca8a7d2..9f2ca8a7d2 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-4GB.inc
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-nanya-2GB.inc
index bd82e7b774..bd82e7b774 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-nanya-2GB.inc
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc
index f5793d1561..f5793d1561 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-4GB.inc
index a32f1a6129..a32f1a6129 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-4GB.inc
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-2GB.inc
index ef82b27781..ef82b27781 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-2GB.inc
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-4GB.inc
index e071646bf4..e071646bf4 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-4GB.inc
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
index 00dc549161..00dc549161 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-4GB.inc
index a48ac42a0e..a48ac42a0e 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-4GB.inc
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc
index 0f15ba5074..0f15ba5074 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
index 09d260bc23..09d260bc23 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc
index 06498f7f14..06498f7f14 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-unused.inc
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc
diff --git a/src/mainboard/google/veyron_jerry/Kconfig.name b/src/mainboard/google/veyron_jerry/Kconfig.name
deleted file mode 100644
index 10c5f4e144..0000000000
--- a/src/mainboard/google/veyron_jerry/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_JERRY
- bool "Veyron_Jerry"
diff --git a/src/mainboard/google/veyron_jerry/board.h b/src/mainboard/google/veyron_jerry/board.h
deleted file mode 100644
index 01be2cd2bc..0000000000
--- a/src/mainboard/google/veyron_jerry/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 2)
-#define GPIO_RESET GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H */
diff --git a/src/mainboard/google/veyron_jerry/mainboard.c b/src/mainboard/google/veyron_jerry/mainboard.c
deleted file mode 100644
index 2a945c48fd..0000000000
--- a/src/mainboard/google/veyron_jerry/mainboard.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- /* Note: these power rail definitions are copied in romstage.c */
- rk808_configure_ldo(4, 3300); /* VCCIO_SD */
- rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
- gpio_input(GPIO(7, A, 5)); /* SD_DET */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- switch (board_id()) {
- case 2:
- rk808_configure_switch(2, 1); /* VCC18_LCD */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- break;
- default:
- gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-
- /* enable edp HPD */
- gpio_input_pulldown(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
- break;
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
-
- elog_init();
- elog_add_watchdog_reset();
- elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- switch (board_id()) {
- case 2:
- gpio_output(GPIO(7, A, 0), 0); /* BL_EN */
- gpio_output(GPIO(7, A, 2), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO(7, A, 0), 1); /* BL_EN */
- break;
- default:
- gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(120);
- gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
- break;
- }
-}
diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig
deleted file mode 100644
index 4dad49cfc3..0000000000
--- a/src/mainboard/google/veyron_mighty/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_MIGHTY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select COMMON_CBFS_SPI_WRAPPER
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select BOARD_ROMSIZE_KB_4096
- select HAVE_HARD_RESET
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select CHROMEOS_VBNV_EC
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_mighty
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Mighty"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
- int
- default 100
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-endif # BOARD_GOOGLE_VEYRON_MIGHTY
diff --git a/src/mainboard/google/veyron_mighty/Kconfig.name b/src/mainboard/google/veyron_mighty/Kconfig.name
deleted file mode 100644
index 0eb4536e36..0000000000
--- a/src/mainboard/google/veyron_mighty/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_MIGHTY
- bool "Veyron_Mighty"
diff --git a/src/mainboard/google/veyron_mighty/Makefile.inc b/src/mainboard/google/veyron_mighty/Makefile.inc
deleted file mode 100644
index ea1c6063e7..0000000000
--- a/src/mainboard/google/veyron_mighty/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_mighty/board.h b/src/mainboard/google/veyron_mighty/board.h
deleted file mode 100644
index 909f9a79d5..0000000000
--- a/src/mainboard/google/veyron_mighty/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_MIGHTY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_MIGHTY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 2)
-#define GPIO_RESET GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_MIGHTY_BOARD_H */
diff --git a/src/mainboard/google/veyron_mighty/boardid.c b/src/mainboard/google/veyron_mighty/boardid.c
deleted file mode 100644
index f7cddcc4fe..0000000000
--- a/src/mainboard/google/veyron_mighty/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
deleted file mode 100644
index ae74972340..0000000000
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
- /* spi0 for chrome ec */
- write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_mighty/chromeos.c b/src/mainboard/google/veyron_mighty/chromeos.c
deleted file mode 100644
index 54896391a8..0000000000
--- a/src/mainboard/google/veyron_mighty/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_LID GPIO(0, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_ECINRW GPIO(0, A, 7)
-#define GPIO_ECIRQ GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
- gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC in RW: GPIO active high */
- gpios->gpios[count].port = GPIO_ECINRW.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC in RW",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC interrupt: GPIO active high */
- gpios->gpios[count].port = GPIO_ECIRQ.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC interrupt",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Reset: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_RESET.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "reset",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Backlight: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "backlight",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_mighty/devicetree.cb b/src/mainboard/google/veyron_mighty/devicetree.cb
deleted file mode 100644
index b958e267d4..0000000000
--- a/src/mainboard/google/veyron_mighty/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_EDP"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_mighty/mainboard.c b/src/mainboard/google/veyron_mighty/mainboard.c
deleted file mode 100644
index d76e2e55cb..0000000000
--- a/src/mainboard/google/veyron_mighty/mainboard.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- /* Note: these power rail definitions are copied in romstage.c */
- rk808_configure_ldo(4, 3300); /* VCCIO_SD */
- rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
- gpio_input(GPIO(7, A, 5)); /* SD_DET */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- switch (board_id()) {
- case 0:
- rk808_configure_switch(2, 1); /* VCC18_LCD */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- break;
- default:
- gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-
- /* enable edp HPD */
- gpio_input_pulldown(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
- break;
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
-
- elog_init();
- elog_add_watchdog_reset();
- elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- switch (board_id()) {
- case 0:
- gpio_output(GPIO(7, A, 0), 0); /* BL_EN */
- gpio_output(GPIO(7, A, 2), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO(7, A, 0), 1); /* BL_EN */
- break;
- default:
- gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(20);
- gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
- break;
- }
-}
diff --git a/src/mainboard/google/veyron_mighty/memlayout.ld b/src/mainboard/google/veyron_mighty/memlayout.ld
deleted file mode 100644
index ead7f47838..0000000000
--- a/src/mainboard/google/veyron_mighty/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_mighty/reset.c b/src/mainboard/google/veyron_mighty/reset.c
deleted file mode 100644
index bc26ece4b3..0000000000
--- a/src/mainboard/google/veyron_mighty/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c
deleted file mode 100644
index 5ccbe3ec23..0000000000
--- a/src/mainboard/google/veyron_mighty/romstage.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
- rk808_configure_ldo(4, 0); /* VCCIO_SD */
- rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_mighty/sdram_configs.c b/src/mainboard/google/veyron_mighty/sdram_configs.c
deleted file mode 100644
index 023eb3772c..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4b88..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a7d2..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b774..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1561..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6129..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b27781..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646bf4..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549161..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 14,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42a0e..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5074..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260bc23..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7f14..0000000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-}, \ No newline at end of file
diff --git a/src/mainboard/google/veyron_minnie/Kconfig b/src/mainboard/google/veyron_minnie/Kconfig
deleted file mode 100644
index f2cd87bba1..0000000000
--- a/src/mainboard/google/veyron_minnie/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_MINNIE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select BOARD_ROMSIZE_KB_4096
- select COMMON_CBFS_SPI_WRAPPER
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select HAVE_HARD_RESET
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select CHROMEOS_VBNV_EC
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_minnie
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Minnie"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
- int
- default 100
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-endif # BOARD_GOOGLE_VEYRON_MINNIE
diff --git a/src/mainboard/google/veyron_minnie/Kconfig.name b/src/mainboard/google/veyron_minnie/Kconfig.name
deleted file mode 100644
index bb7b75e7a0..0000000000
--- a/src/mainboard/google/veyron_minnie/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_MINNIE
- bool "Veyron_Minnie"
diff --git a/src/mainboard/google/veyron_minnie/Makefile.inc b/src/mainboard/google/veyron_minnie/Makefile.inc
deleted file mode 100644
index ea1c6063e7..0000000000
--- a/src/mainboard/google/veyron_minnie/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_minnie/board.h b/src/mainboard/google/veyron_minnie/board.h
deleted file mode 100644
index 07b302bfd4..0000000000
--- a/src/mainboard/google/veyron_minnie/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_MINNIE_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_MINNIE_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 2)
-#define GPIO_RESET GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_MINNIE_BOARD_H */
diff --git a/src/mainboard/google/veyron_minnie/board_info.txt b/src/mainboard/google/veyron_minnie/board_info.txt
deleted file mode 100644
index 4ce92d3812..0000000000
--- a/src/mainboard/google/veyron_minnie/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: laptop
diff --git a/src/mainboard/google/veyron_minnie/boardid.c b/src/mainboard/google/veyron_minnie/boardid.c
deleted file mode 100644
index f7cddcc4fe..0000000000
--- a/src/mainboard/google/veyron_minnie/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_minnie/bootblock.c b/src/mainboard/google/veyron_minnie/bootblock.c
deleted file mode 100644
index ae74972340..0000000000
--- a/src/mainboard/google/veyron_minnie/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
- /* spi0 for chrome ec */
- write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_minnie/chromeos.c b/src/mainboard/google/veyron_minnie/chromeos.c
deleted file mode 100644
index 54896391a8..0000000000
--- a/src/mainboard/google/veyron_minnie/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_LID GPIO(0, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_ECINRW GPIO(0, A, 7)
-#define GPIO_ECIRQ GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
- gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC in RW: GPIO active high */
- gpios->gpios[count].port = GPIO_ECINRW.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC in RW",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC interrupt: GPIO active high */
- gpios->gpios[count].port = GPIO_ECIRQ.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC interrupt",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Reset: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_RESET.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "reset",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Backlight: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "backlight",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_minnie/devicetree.cb b/src/mainboard/google/veyron_minnie/devicetree.cb
deleted file mode 100644
index b958e267d4..0000000000
--- a/src/mainboard/google/veyron_minnie/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_EDP"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_minnie/memlayout.ld b/src/mainboard/google/veyron_minnie/memlayout.ld
deleted file mode 100644
index ead7f47838..0000000000
--- a/src/mainboard/google/veyron_minnie/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_minnie/reset.c b/src/mainboard/google/veyron_minnie/reset.c
deleted file mode 100644
index bc26ece4b3..0000000000
--- a/src/mainboard/google/veyron_minnie/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c
deleted file mode 100644
index 9cdacc3e1a..0000000000
--- a/src/mainboard/google/veyron_minnie/romstage.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
- rk808_configure_ldo(4, 0); /* VCCIO_SD */
- rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_minnie/sdram_configs.c b/src/mainboard/google/veyron_minnie/sdram_configs.c
deleted file mode 100644
index 023eb3772c..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4b88..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a7d2..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b774..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1561..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6129..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b27781..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646bf4..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549161..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 14,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42a0e..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5074..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260bc23..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7f14..0000000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-}, \ No newline at end of file
diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig
deleted file mode 100644
index 5c6e7cd015..0000000000
--- a/src/mainboard/google/veyron_pinky/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_PINKY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select COMMON_CBFS_SPI_WRAPPER
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select BOARD_ROMSIZE_KB_4096
- select HAVE_HARD_RESET
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select CHROMEOS_VBNV_EC
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_pinky
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Pinky"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
- int
- default 100
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-endif # BOARD_GOOGLE_VEYRON_PINKY
diff --git a/src/mainboard/google/veyron_pinky/Kconfig.name b/src/mainboard/google/veyron_pinky/Kconfig.name
deleted file mode 100644
index 37d92f2e9b..0000000000
--- a/src/mainboard/google/veyron_pinky/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_PINKY
- bool "Veyron_Pinky"
diff --git a/src/mainboard/google/veyron_pinky/Makefile.inc b/src/mainboard/google/veyron_pinky/Makefile.inc
deleted file mode 100644
index a41b3bfee6..0000000000
--- a/src/mainboard/google/veyron_pinky/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += romstage.c
-romstage-y += chromeos.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_pinky/board.h b/src/mainboard/google/veyron_pinky/board.h
deleted file mode 100644
index 24690df050..0000000000
--- a/src/mainboard/google/veyron_pinky/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 2)
-#define GPIO_RESET (board_id() > 0 ? GPIO(0, B, 5) : GPIO(0, B, 2))
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H */
diff --git a/src/mainboard/google/veyron_pinky/boardid.c b/src/mainboard/google/veyron_pinky/boardid.c
deleted file mode 100644
index f7cddcc4fe..0000000000
--- a/src/mainboard/google/veyron_pinky/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
deleted file mode 100644
index ae74972340..0000000000
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
- /* spi0 for chrome ec */
- write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_pinky/chromeos.c b/src/mainboard/google/veyron_pinky/chromeos.c
deleted file mode 100644
index 5e81dad89d..0000000000
--- a/src/mainboard/google/veyron_pinky/chromeos.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_LID (board_id() > 0 ? GPIO(0, A, 6) : GPIO(7, B, 5))
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_ECINRW GPIO(0, A, 7)
-#define GPIO_ECIRQ GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
- gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = board_id() > 1 ? ACTIVE_LOW :
- ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC in RW: GPIO active high */
- gpios->gpios[count].port = GPIO_ECINRW.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC in RW",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC interrupt: GPIO active high */
- gpios->gpios[count].port = GPIO_ECIRQ.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC interrupt",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Reset: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_RESET.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "reset",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Backlight: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "backlight",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_pinky/devicetree.cb b/src/mainboard/google/veyron_pinky/devicetree.cb
deleted file mode 100644
index b958e267d4..0000000000
--- a/src/mainboard/google/veyron_pinky/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_EDP"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
deleted file mode 100644
index 2caa2be523..0000000000
--- a/src/mainboard/google/veyron_pinky/mainboard.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
-
- switch (board_id()) {
- case 0:
- gpio_output(GPIO(7, B, 3), 1); /* 5V_DRV */
- break;
- case 1:
- break; /* 5V_DRV moved to EC in rev2 */
- default:
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV, again */
- break;
- }
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- /* Note: these power rail definitions are copied in romstage.c */
- switch (board_id()) {
- case 0:
- rk808_configure_ldo(8, 3300); /* VCCIO_SD */
- gpio_output(GPIO(7, C, 5), 1); /* SD_EN */
- break;
- default:
- rk808_configure_ldo(4, 3300); /* VCCIO_SD */
- rk808_configure_ldo(5, 3300); /* VCC33_SD */
- break;
- }
-
- gpio_input(GPIO(7, A, 5)); /* SD_DET */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- switch (board_id()) {
- case 0:
- case 1:
- /*
- * Use a pullup instead of a drive since the output is 3.3V and
- * really should be 1.8V (oops). The external pulldown will help
- * bring the voltage down if we only drive with a pullup here.
- */
- gpio_input_pullup(GPIO(7, B, 4)); /* EMMC_RST_L */
- break;
- default:
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
- break;
- }
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- switch (board_id()) {
- case 0:
- rk808_configure_ldo(5, 1800); /* VCC18_CODEC */
- break;
- default:
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
- break;
- }
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- switch (board_id()) {
- case 0:
- rk808_configure_ldo(4, 1800); /* VCC18_LCD */
- rk808_configure_ldo(6, 1000); /* VCC10_LCD */
- gpio_output(GPIO(7, B, 7), 1); /* LCD_EN */
- break;
- case 1:
- case 2:
- rk808_configure_switch(2, 1); /* VCC18_LCD */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- break;
- default:
- gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
-
- /* enable edp HPD */
- gpio_input_pulldown(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
- break;
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
-
- elog_init();
- elog_add_watchdog_reset();
- elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- switch (board_id()) {
- case 0:
- case 1:
- case 2:
- gpio_output(GPIO(7, A, 0), 0); /* BL_EN */
- gpio_output(GPIO(7, A, 2), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO(7, A, 0), 1); /* BL_EN */
- break;
- default:
- gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(20);
- gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
- break;
- }
-}
diff --git a/src/mainboard/google/veyron_pinky/memlayout.ld b/src/mainboard/google/veyron_pinky/memlayout.ld
deleted file mode 100644
index ead7f47838..0000000000
--- a/src/mainboard/google/veyron_pinky/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_pinky/reset.c b/src/mainboard/google/veyron_pinky/reset.c
deleted file mode 100644
index bc26ece4b3..0000000000
--- a/src/mainboard/google/veyron_pinky/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c
deleted file mode 100644
index 3792e6273a..0000000000
--- a/src/mainboard/google/veyron_pinky/romstage.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
- switch (board_id()) {
- case 0:
- rk808_configure_ldo(8, 0); /* VCCIO_SD */
- gpio_output(GPIO(7, C, 5), 0); /* SD_EN */
- break;
- default:
- rk808_configure_ldo(4, 0); /* VCCIO_SD */
- rk808_configure_ldo(5, 0); /* VCC33_SD */
- break;
- }
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c
deleted file mode 100644
index 023eb3772c..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4b88..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a7d2..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b774..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1561..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6129..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b27781..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646bf4..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549161..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 14,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42a0e..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5074..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260bc23..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7f14..0000000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-}, \ No newline at end of file
diff --git a/src/mainboard/google/veyron_shark/Kconfig b/src/mainboard/google/veyron_shark/Kconfig
deleted file mode 100644
index 829fb85243..0000000000
--- a/src/mainboard/google/veyron_shark/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_SHARK
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select BOARD_ROMSIZE_KB_4096
- select COMMON_CBFS_SPI_WRAPPER
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select HAVE_HARD_RESET
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select CHROMEOS_VBNV_EC
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_shark
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Shark"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
- int
- default 100
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-endif # BOARD_GOOGLE_VEYRON_SHARK
diff --git a/src/mainboard/google/veyron_shark/Kconfig.name b/src/mainboard/google/veyron_shark/Kconfig.name
deleted file mode 100644
index 16c82a92a3..0000000000
--- a/src/mainboard/google/veyron_shark/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_SHARK
- bool "Veyron_Shark"
diff --git a/src/mainboard/google/veyron_shark/Makefile.inc b/src/mainboard/google/veyron_shark/Makefile.inc
deleted file mode 100644
index ea1c6063e7..0000000000
--- a/src/mainboard/google/veyron_shark/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_shark/boardid.c b/src/mainboard/google/veyron_shark/boardid.c
deleted file mode 100644
index f7cddcc4fe..0000000000
--- a/src/mainboard/google/veyron_shark/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_shark/bootblock.c b/src/mainboard/google/veyron_shark/bootblock.c
deleted file mode 100644
index ae74972340..0000000000
--- a/src/mainboard/google/veyron_shark/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
- /* spi0 for chrome ec */
- write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_shark/chromeos.c b/src/mainboard/google/veyron_shark/chromeos.c
deleted file mode 100644
index 54896391a8..0000000000
--- a/src/mainboard/google/veyron_shark/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_LID GPIO(0, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_ECINRW GPIO(0, A, 7)
-#define GPIO_ECIRQ GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
- gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC in RW: GPIO active high */
- gpios->gpios[count].port = GPIO_ECINRW.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC in RW",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC interrupt: GPIO active high */
- gpios->gpios[count].port = GPIO_ECIRQ.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC interrupt",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Reset: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_RESET.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "reset",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Backlight: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "backlight",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_shark/devicetree.cb b/src/mainboard/google/veyron_shark/devicetree.cb
deleted file mode 100644
index b958e267d4..0000000000
--- a/src/mainboard/google/veyron_shark/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_EDP"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_shark/mainboard.c b/src/mainboard/google/veyron_shark/mainboard.c
deleted file mode 100644
index c8cb248caa..0000000000
--- a/src/mainboard/google/veyron_shark/mainboard.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- /* Note: these power rail definitions are copied in romstage.c */
- rk808_configure_ldo(4, 3300); /* VCCIO_SD */
- rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
- gpio_input(GPIO(7, A, 5)); /* SD_DET */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- switch (board_id()) {
- case 0:
- rk808_configure_switch(2, 1); /* VCC18_LCD */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- break;
- default:
- gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-
- /* enable edp HPD */
- gpio_input_pulldown(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
- break;
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
-
- elog_init();
- elog_add_watchdog_reset();
- elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(20);
- gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
-}
diff --git a/src/mainboard/google/veyron_shark/memlayout.ld b/src/mainboard/google/veyron_shark/memlayout.ld
deleted file mode 100644
index ead7f47838..0000000000
--- a/src/mainboard/google/veyron_shark/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_shark/reset.c b/src/mainboard/google/veyron_shark/reset.c
deleted file mode 100644
index bc26ece4b3..0000000000
--- a/src/mainboard/google/veyron_shark/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_shark/romstage.c b/src/mainboard/google/veyron_shark/romstage.c
deleted file mode 100644
index 9cdacc3e1a..0000000000
--- a/src/mainboard/google/veyron_shark/romstage.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
- rk808_configure_ldo(4, 0); /* VCCIO_SD */
- rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_shark/sdram_configs.c b/src/mainboard/google/veyron_shark/sdram_configs.c
deleted file mode 100644
index 023eb3772c..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4b88..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a7d2..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b774..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1561..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6129..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b27781..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646bf4..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549161..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 14,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42a0e..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5074..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260bc23..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7f14..0000000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-}, \ No newline at end of file
diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig
deleted file mode 100644
index 411ea426be..0000000000
--- a/src/mainboard/google/veyron_speedy/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_SPEEDY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select BOARD_ROMSIZE_KB_4096
- select COMMON_CBFS_SPI_WRAPPER
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select HAVE_HARD_RESET
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select CHROMEOS_VBNV_EC
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_speedy
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Speedy"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
- int
- default 100
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-endif # BOARD_GOOGLE_VEYRON_SPEEDY
diff --git a/src/mainboard/google/veyron_speedy/Kconfig.name b/src/mainboard/google/veyron_speedy/Kconfig.name
deleted file mode 100644
index a5b2c9da41..0000000000
--- a/src/mainboard/google/veyron_speedy/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_SPEEDY
- bool "Veyron_Speedy"
diff --git a/src/mainboard/google/veyron_speedy/Makefile.inc b/src/mainboard/google/veyron_speedy/Makefile.inc
deleted file mode 100644
index ea1c6063e7..0000000000
--- a/src/mainboard/google/veyron_speedy/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_speedy/board.h b/src/mainboard/google/veyron_speedy/board.h
deleted file mode 100644
index ee705df3c1..0000000000
--- a/src/mainboard/google/veyron_speedy/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 2)
-#define GPIO_RESET GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H */
diff --git a/src/mainboard/google/veyron_speedy/boardid.c b/src/mainboard/google/veyron_speedy/boardid.c
deleted file mode 100644
index f7cddcc4fe..0000000000
--- a/src/mainboard/google/veyron_speedy/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
deleted file mode 100644
index ae74972340..0000000000
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
- /* spi0 for chrome ec */
- write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_speedy/chromeos.c b/src/mainboard/google/veyron_speedy/chromeos.c
deleted file mode 100644
index 54896391a8..0000000000
--- a/src/mainboard/google/veyron_speedy/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_LID GPIO(0, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_ECINRW GPIO(0, A, 7)
-#define GPIO_ECIRQ GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
- gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC in RW: GPIO active high */
- gpios->gpios[count].port = GPIO_ECINRW.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC in RW",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC interrupt: GPIO active high */
- gpios->gpios[count].port = GPIO_ECIRQ.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC interrupt",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Reset: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_RESET.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "reset",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Backlight: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "backlight",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_speedy/devicetree.cb b/src/mainboard/google/veyron_speedy/devicetree.cb
deleted file mode 100644
index b958e267d4..0000000000
--- a/src/mainboard/google/veyron_speedy/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_EDP"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_speedy/mainboard.c b/src/mainboard/google/veyron_speedy/mainboard.c
deleted file mode 100644
index d76e2e55cb..0000000000
--- a/src/mainboard/google/veyron_speedy/mainboard.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- /* Note: these power rail definitions are copied in romstage.c */
- rk808_configure_ldo(4, 3300); /* VCCIO_SD */
- rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
- gpio_input(GPIO(7, A, 5)); /* SD_DET */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- switch (board_id()) {
- case 0:
- rk808_configure_switch(2, 1); /* VCC18_LCD */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- break;
- default:
- gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-
- /* enable edp HPD */
- gpio_input_pulldown(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
- break;
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
-
- elog_init();
- elog_add_watchdog_reset();
- elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- switch (board_id()) {
- case 0:
- gpio_output(GPIO(7, A, 0), 0); /* BL_EN */
- gpio_output(GPIO(7, A, 2), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO(7, A, 0), 1); /* BL_EN */
- break;
- default:
- gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(20);
- gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
- break;
- }
-}
diff --git a/src/mainboard/google/veyron_speedy/memlayout.ld b/src/mainboard/google/veyron_speedy/memlayout.ld
deleted file mode 100644
index ead7f47838..0000000000
--- a/src/mainboard/google/veyron_speedy/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_speedy/reset.c b/src/mainboard/google/veyron_speedy/reset.c
deleted file mode 100644
index bc26ece4b3..0000000000
--- a/src/mainboard/google/veyron_speedy/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c
deleted file mode 100644
index 9cdacc3e1a..0000000000
--- a/src/mainboard/google/veyron_speedy/romstage.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
- rk808_configure_ldo(4, 0); /* VCCIO_SD */
- rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_speedy/sdram_configs.c b/src/mainboard/google/veyron_speedy/sdram_configs.c
deleted file mode 100644
index 023eb3772c..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4b88..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a7d2..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b774..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1561..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6129..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b27781..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646bf4..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549161..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 14,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42a0e..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5074..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260bc23..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7f14..0000000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-}, \ No newline at end of file