summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/cpu/x86/tsc/delay_tsc.c4
-rw-r--r--src/mainboard/eaglelion/5bcm/Options.lb7
2 files changed, 11 insertions, 0 deletions
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index c7c431baac..31c5bf80eb 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -159,7 +159,11 @@ void udelay(unsigned us)
count = rdtscll();
stop = clocks + count;
while(stop > count) {
+#ifdef CONFIG_SMP
+#if CONFIG_SMP == 1
cpu_relax();
+#endif
+#endif
count = rdtscll();
}
}
diff --git a/src/mainboard/eaglelion/5bcm/Options.lb b/src/mainboard/eaglelion/5bcm/Options.lb
index 1c87e9f244..df3d1bdfb6 100644
--- a/src/mainboard/eaglelion/5bcm/Options.lb
+++ b/src/mainboard/eaglelion/5bcm/Options.lb
@@ -37,6 +37,8 @@ uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -60,6 +62,11 @@ default HAVE_MP_TABLE=0
##
default HAVE_HARD_RESET=0
+## Delay timer options
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
##
## Build code to export a programmable irq routing table
##