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-rw-r--r--src/mainboard/google/cyan/romstage.c1
-rw-r--r--src/mainboard/intel/strago/romstage.c1
-rw-r--r--src/soc/intel/braswell/chip.h3
-rw-r--r--src/soc/intel/braswell/include/soc/romstage.h4
4 files changed, 4 insertions, 5 deletions
diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c
index aa20593d5f..5470b9c465 100644
--- a/src/mainboard/google/cyan/romstage.c
+++ b/src/mainboard/google/cyan/romstage.c
@@ -16,7 +16,6 @@
#include <soc/romstage.h>
#include <baseboard/variants.h>
-#include <chip.h>
/* All FSP specific code goes in this block */
void mainboard_romstage_entry(struct romstage_params *rp)
diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c
index 0f3067ea81..ba0ff7b85e 100644
--- a/src/mainboard/intel/strago/romstage.c
+++ b/src/mainboard/intel/strago/romstage.c
@@ -17,7 +17,6 @@
#include <soc/gpio.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
-#include <chip.h>
#include "onboard.h"
#include <boardid.h>
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index bb06dd595a..5a00328f4d 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -32,9 +32,6 @@
#define SVID_CONFIG3 3
#define SVID_PMIC_CONFIG 8
-#define MEM_DDR3 0
-#define MEM_LPDDR3 1
-
enum lpe_clk_src {
LPE_CLK_SRC_XTAL,
LPE_CLK_SRC_PLL,
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 8fa9c8a713..2512430f75 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -34,4 +34,8 @@ void set_max_freq(void);
void program_base_addresses(void);
int chipset_prev_sleep_state(struct chipset_power_state *ps);
+/* Values for FSP's PcdMemoryTypeEnable */
+#define MEM_DDR3 0
+#define MEM_LPDDR3 1
+
#endif /* _SOC_ROMSTAGE_H_ */