diff options
| -rw-r--r-- | src/lib/debug.c | 96 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dx/tco_timer.c | 31 | ||||
| -rw-r--r-- | src/superio/smsc/lpc47b397/early_gpio.c | 45 |
3 files changed, 0 insertions, 172 deletions
diff --git a/src/lib/debug.c b/src/lib/debug.c deleted file mode 100644 index 80ee416b93..0000000000 --- a/src/lib/debug.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void print_debug_pci_dev(unsigned int dev) -{ - printk(BIOS_DEBUG, "PCI: %02x:%02x.%x", - (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7); -} - -static inline void print_pci_devices(void) -{ -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev; -#else - struct device *dev; -#endif - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0x00, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) - || (((id >> 16) & 0xffff) == 0xffff) - || (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, "\n"); - } -} - -static void dump_pci_device(unsigned int dev) -{ - int i; - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, "\n"); - - for (i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "%02x:", i); - val = pci_read_config8(dev, i); - printk(BIOS_DEBUG, " %02x", val); - if ((i & 0x0f) == 0x0f) - printk(BIOS_DEBUG, "\n"); - } -} - -static inline void dump_pci_devices(void) -{ -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev; -#else - struct device *dev; -#endif - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) - || (((id >> 16) & 0xffff) == 0xffff) - || (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - - -static inline void dump_io_resources(unsigned int port) -{ - int i; - printk(BIOS_DEBUG, "%04x:\n", port); - for (i = 0; i < 256; i++) { - u8 val; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "%02x:", i); - val = inb(port); - printk(BIOS_DEBUG, " %02x", val); - if ((i & 0x0f) == 0x0f) - printk(BIOS_DEBUG, "\n"); - port++; - } -} diff --git a/src/southbridge/intel/i82801dx/tco_timer.c b/src/southbridge/intel/i82801dx/tco_timer.c deleted file mode 100644 index e773fa47d7..0000000000 --- a/src/southbridge/intel/i82801dx/tco_timer.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void i82801dx_halt_tco_timer(void) -{ - /* Set the LPC device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Temporarily set ACPI base address (I/O space). */ - pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - - /* Enable ACPI I/O. */ - pci_write_config8(dev, ACPI_CNTL, 0x10); - - /* Halt the TCO timer, preventing SMI and automatic reboot */ - outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), - PMBASE_ADDR + TCOBASE + TCO1_CNT); -} diff --git a/src/superio/smsc/lpc47b397/early_gpio.c b/src/superio/smsc/lpc47b397/early_gpio.c deleted file mode 100644 index 66a040cfff..0000000000 --- a/src/superio/smsc/lpc47b397/early_gpio.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value) -{ - outb(value, iobase + offset); -} - -static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset) -{ - return inb(iobase+offset); -} - -#if 0 -/* For GP60-GP64, GP66-GP85. */ -#define LPC47B397_GPIO_CNTL_INDEX 0x70 -#define LPC47B397_GPIO_CNTL_DATA 0x71 - -static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value) -{ - outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); - outb(value, iobase + LPC47B397_GPIO_CNTL_DATA); -} - -static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index) -{ - outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); - return inb(iobase + LPC47B397_GPIO_CNTL_DATA); -} -#endif |