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-rw-r--r--src/northbridge/intel/haswell/fffcbf28.asm18
-rw-r--r--src/northbridge/intel/haswell/mrc_misc.c15
-rw-r--r--src/northbridge/intel/haswell/mrc_misc.h6
3 files changed, 21 insertions, 18 deletions
diff --git a/src/northbridge/intel/haswell/fffcbf28.asm b/src/northbridge/intel/haswell/fffcbf28.asm
index a68b9cea93..ce8479be18 100644
--- a/src/northbridge/intel/haswell/fffcbf28.asm
+++ b/src/northbridge/intel/haswell/fffcbf28.asm
@@ -1,9 +1,9 @@
global ref_fffcbf28
-extern fcn_fffaa884
-extern fcn_fffaa6af
-extern fcn_fffa78a0
-extern fcn_fffb8689
+extern MrcFastBootPermitted
+extern MrcRestoreNonTrainingValues
+extern MrcMcCapabilityPreSpd
+extern MrcSpdProcessing
extern fcn_fffa782c
extern fcn_fffa7a1c
extern fcn_fffa56ac
@@ -54,19 +54,19 @@ extern fcn_fffa8fb6
extern dummy_func
ref_fffcbf28:
-dd fcn_fffaa884
+dd MrcFastBootPermitted
dd 0x0000dd1b
dd 0xff320000
-dd fcn_fffaa6af
+dd MrcRestoreNonTrainingValues
dd 0x0001dd1c
dd 0xff3e0000
-dd dummy_func
+dd dummy_func ; MrcSetOverridesPreSpd
dd 0x0004dd1e
dd 0xff3f0000
-dd fcn_fffa78a0
+dd MrcMcCapabilityPreSpd
dd 0x0005dd1f
dd 0xff3f0000
-dd fcn_fffb8689
+dd MrcSpdProcessing
dd 0x0003dd20
dd 0xff310000
dd fcn_fffa782c
diff --git a/src/northbridge/intel/haswell/mrc_misc.c b/src/northbridge/intel/haswell/mrc_misc.c
index de58ab9bfb..04707677cd 100644
--- a/src/northbridge/intel/haswell/mrc_misc.c
+++ b/src/northbridge/intel/haswell/mrc_misc.c
@@ -102,8 +102,8 @@ int fcn_fffbd29a(void * a0, void * a1, void * a2)
}
}
-int fcn_fffaa884(void *ram_data);
-int fcn_fffaa884(void *ram_data)
+int MrcFastBootPermitted(void *ram_data);
+int MrcFastBootPermitted(void *ram_data)
{
void *bar = *(void**)(ram_data + 0x103b);
@@ -964,7 +964,8 @@ fcn_fffb5038(void *ram_data,uint32_t *param_2,uint8_t *param_3,uint32_t *param_4
return memcfg_clk;
}
-int fcn_fffaa6af(void *ram_data)
+// fcn_fffaa6af
+int MrcRestoreNonTrainingValues(void *ram_data)
{
PRINT_FUNC;
@@ -1015,7 +1016,8 @@ extern uint8_t ref_fffcbc04[];
// CAPID0_A 0xe4 is already defined
#define CAPID0_B 0xe8
-int fcn_fffa78a0(void *ramdata)
+// fcn_fffa78a0
+int MrcMcCapabilityPreSpd(void *ramdata)
{
uint64_t lVar1;
uint32_t uVar2;
@@ -1127,7 +1129,8 @@ static bool is_zero256(const void *data)
return true;
}
-int fcn_fffb8689(void *ramdata)
+// fcn_fffb8689
+int MrcSpdProcessing(void *ramdata)
{
char cVar2;
uint32_t uVar4;
@@ -1144,7 +1147,7 @@ int fcn_fffb8689(void *ramdata)
local_78 = 0;
local_84 = 0;
local_7c = 0;
- local_80 = 0x16;
+ local_80 = 0x16; // mrcDimmNotExist
do {
iVar8 = local_78 * 0x2fa;
for (int idx = 0; idx < 2; idx++) {
diff --git a/src/northbridge/intel/haswell/mrc_misc.h b/src/northbridge/intel/haswell/mrc_misc.h
index ecd12aa7ef..37ca1ec67d 100644
--- a/src/northbridge/intel/haswell/mrc_misc.h
+++ b/src/northbridge/intel/haswell/mrc_misc.h
@@ -12,8 +12,8 @@ uint64_t MRCABI
fcn_fffb5038(void *ram_data,uint32_t *param_2,uint8_t *param_3,uint32_t *param_4);
uint64_t udiv64(uint64_t, uint64_t);
-int fcn_fffaa6af(void *ram_data);
-int fcn_fffa78a0(void *ramdata);
+int MrcRestoreNonTrainingValues(void *ram_data);
+int MrcMcCapabilityPreSpd(void *ramdata);
typedef int (*callback_t)(void *);
typedef int (*callback3_t)(void *, void *, void *);
@@ -53,7 +53,7 @@ DECL_CB1(fcn_fffb7c94);
DECL_CB1(fcn_fffb7acc);
DECL_CB1(fcn_fffb7866);
-int fcn_fffb8689(void *ramdata);
+int MrcSpdProcessing(void *ramdata);
int fcn_fffa7a1c(void *ramdata);
int fcn_fffc7720(void *ramdata);
int MRCABI wait_5030(void *ramdata);