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-rw-r--r--src/commonlib/include/commonlib/cbmem_id.h4
-rw-r--r--src/soc/intel/common/gma.h154
-rw-r--r--src/soc/intel/common/opregion.c20
3 files changed, 129 insertions, 49 deletions
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
index 9fb1606528..f6233b3827 100644
--- a/src/commonlib/include/commonlib/cbmem_id.h
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -68,6 +68,7 @@
#define CBMEM_ID_VPD 0x56504420
#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
#define CBMEM_ID_EC_HOSTEVENT 0x63ccbbc3
+#define CBMEM_ID_EXT_VBT 0x69866684
#define CBMEM_ID_TO_NAME_TABLE \
{ CBMEM_ID_ACPI, "ACPI " }, \
@@ -116,5 +117,6 @@
{ CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \
{ CBMEM_ID_VPD, "VPD " }, \
{ CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " }, \
- { CBMEM_ID_EC_HOSTEVENT, "EC HOSTEVENT"},
+ { CBMEM_ID_EC_HOSTEVENT, "EC HOSTEVENT"}, \
+ { CBMEM_ID_EXT_VBT, "EXT VBT"},
#endif /* _CBMEM_ID_H_ */
diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h
index c019286065..db09ca8698 100644
--- a/src/soc/intel/common/gma.h
+++ b/src/soc/intel/common/gma.h
@@ -19,6 +19,7 @@
#define _COMMON_GMA_H_
#include <types.h>
+#include <commonlib/helpers.h>
/* IGD PCI Configuration register */
#define ASLS 0xfc /* OpRegion Base */
@@ -28,14 +29,17 @@
/* mailbox 0: header */
typedef struct {
- u8 signature[16];
- u32 size;
- u32 version;
- u8 sbios_version[32];
- u8 vbios_version[16];
- u8 driver_version[16];
- u32 mailboxes;
- u8 reserved[164];
+ u8 signature[16]; /* Offset 0 OpRegion signature */
+ u32 size; /* Offset 16 OpRegion size */
+ u32 version; /* Offset 20 OpRegion structure version */
+ u8 sbios_version[32]; /* Offset 24 System BIOS build version */
+ u8 vbios_version[16]; /* Offset 56 Video BIOS build version */
+ u8 driver_version[16]; /* Offset 72 Graphic driver build version */
+ u32 mailboxes; /* Offset 88 Mailboxes supported */
+ u32 dmod; /* Offset 92 Driver Model */
+ u32 pcon; /* Offset 96 Platform Capabilities */
+ u16 dver[16]; /* Offset 100 GOP Version */
+ u8 reserved[124]; /* Offset 132 Reserved */
} __attribute__((packed)) opregion_header_t;
#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
@@ -55,51 +59,100 @@ typedef struct {
/* mailbox 1: public ACPI methods */
typedef struct {
- u32 drdy;
- u32 csts;
- u32 cevt;
- u8 reserved1[20];
- u32 didl[8];
- u32 cpdl[8];
- u32 cadl[8];
- u32 nadl[8];
- u32 aslp;
- u32 tidx;
- u32 chpd;
- u32 clid;
- u32 cdck;
- u32 sxsw;
- u32 evts;
- u32 cnot;
- u32 nrdy;
- u8 reserved2[60];
+ u32 drdy; /* Offset 0 Driver readiness */
+ u32 csts; /* Offset 4 Status */
+ u32 cevt; /* Offset 8 Current event */
+ u8 reserved[20]; /* Offset 12 Reserved */
+ u32 didl; /* Offset 32 Supported display device 1 */
+ u32 ddl2; /* Offset 36 Supported display device 2 */
+ u32 ddl3; /* Offset 40 Supported display device 3 */
+ u32 ddl4; /* Offset 44 Supported display device 4 */
+ u32 ddl5; /* Offset 48 Supported display device 5 */
+ u32 ddl6; /* Offset 52 Supported display device 6 */
+ u32 ddl7; /* Offset 56 Supported display device 7 */
+ u32 ddl8; /* Offset 60 Supported display device 8 */
+ u32 cpdl; /* Offset 64 Currently present display device 1 */
+ u32 cpl2; /* Offset 68 Currently present display device 2 */
+ u32 cpl3; /* Offset 72 Currently present display device 3 */
+ u32 cpl4; /* Offset 76 Currently present display device 4 */
+ u32 cpl5; /* Offset 80 Currently present display device 5 */
+ u32 cpl6; /* Offset 84 Currently present display device 6 */
+ u32 cpl7; /* Offset 88 Currently present display device 7 */
+ u32 cpl8; /* Offset 92 Currently present display device 8 */
+ u32 cadl; /* Offset 96 Currently active display device 1 */
+ u32 cal2; /* Offset 100 Currently active display device 2 */
+ u32 cal3; /* Offset 104 Currently active display device 3 */
+ u32 cal4; /* Offset 108 Currently active display device 4 */
+ u32 cal5; /* Offset 112 Currently active display device 5 */
+ u32 cal6; /* Offset 116 Currently active display device 6 */
+ u32 cal7; /* Offset 120 Currently active display device 7 */
+ u32 cal8; /* Offset 124 Currently active display device 8 */
+ u32 nadl; /* Offset 128 Next active device 1 */
+ u32 ndl2; /* Offset 132 Next active device 2 */
+ u32 ndl3; /* Offset 136 Next active device 3 */
+ u32 ndl4; /* Offset 140 Next active device 4 */
+ u32 ndl5; /* Offset 144 Next active device 5 */
+ u32 ndl6; /* Offset 148 Next active device 6 */
+ u32 ndl7; /* Offset 152 Next active device 7 */
+ u32 ndl8; /* Offset 156 Next active device 8 */
+ u32 aslp; /* Offset 160 ASL sleep timeout */
+ u32 tidx; /* Offset 164 Toggle table index */
+ u32 chpd; /* Offset 168 Current hot plug enable indicator */
+ u32 clid; /* Offset 172 Current lid state indicator */
+ u32 cdck; /* Offset 176 Current docking state indicator */
+ u32 sxsw; /* Offset 180 Display Switch notification on Sx State resume */
+ u32 evts; /* Offset 184 Events supported by ASL */
+ u32 cnot; /* Offset 188 Current OS Notification */
+ u32 nrdy; /* Offset 192 Reasons for DRDY = 0 */
+ u32 ddl9; /* Offset 196 Extended Supported display device 1 */
+ u32 dd10; /* Offset 200 Extended Supported display device 2 */
+ u32 dd11; /* Offset 204 Extended Supported display device 3 */
+ u32 dd12; /* Offset 208 Extended Supported display device 4 */
+ u32 dd13; /* Offset 212 Extended Supported display device 5 */
+ u32 dd14; /* Offset 216 Extended Supported display device 6 */
+ u32 dd15; /* Offset 220 Extended Supported display device 7 */
+ u32 cpl9; /* Offset 224 Extended Currently present device 1 */
+ u32 cp10; /* Offset 228 Extended Currently present device 2 */
+ u32 cp11; /* Offset 232 Extended Currently present device 3 */
+ u32 cp12; /* Offset 236 Extended Currently present device 4 */
+ u32 cp13; /* Offset 240 Extended Currently present device 5 */
+ u32 cp14; /* Offset 244 Extended Currently present device 6 */
+ u32 cp15; /* Offset 248 Extended Currently present device 7 */
+ u8 reserved2[4]; /* Offset 252 Reserved 4 bytes */
} __attribute__((packed)) opregion_mailbox1_t;
/* mailbox 2: software sci interface */
typedef struct {
- u32 scic;
- u32 parm;
- u32 dslp;
- u8 reserved[244];
+ u32 scic; /* Offset 0 Software SCI function number parameters */
+ u32 parm; /* Offset 0 Software SCI function number parameters */
+ u32 dslp; /* Offset 8 Driver sleep timeout */
+ u8 reserved[244]; /* Offset 12 Reserved */
} __attribute__((packed)) opregion_mailbox2_t;
/* mailbox 3: power conservation */
typedef struct {
- u32 ardy;
- u32 aslc;
- u32 tche;
- u32 alsi;
- u32 bclp;
- u32 pfit;
- u32 cblv;
- u16 bclm[20];
- u32 cpfm;
- u32 epfm;
- u8 plut[74];
- u32 pfmb;
- u32 ccdv;
- u32 pcft;
- u8 reserved[94];
+ u32 ardy; /* Offset 0 Driver readiness */
+ u32 aslc; /* Offset 4 ASLE interrupt command / status */
+ u32 tche; /* Offset 8 Technology enabled indicator */
+ u32 alsi; /* Offset 12 Current ALS illuminance reading */
+ u32 bclp; /* Offset 16 Backlight britness to set */
+ u32 pfit; /* Offset 20 Panel fitting Request */
+ u32 cblv; /* Offset 24 Brightness Current State */
+ u16 bclm[20]; /* Offset 28 Backlight Brightness Level Duty Cycle Mapping Table */
+ u32 cpfm; /* Offset 68 Panel Fitting Current Mode */
+ u32 epfm; /* Offset 72 Enabled Panel Fitting Modes */
+ u8 plut[74]; /* Offset 76 Panel Look Up Table */
+ u32 pfmb; /* Offset 150 PWM Frequency and Minimum Brightness */
+ u32 ccdv; /* Offset 154 Color Correction Default Values */
+ u32 pcft; /* Offset 158 Power Conservation Features */
+ u32 srot; /* Offset 162 Supported Rotation angle */
+ u32 iuer; /* Offset 166 Intel Ultrabook Event Register */
+ u64 fdsp; /* Offset 170 FFS Display Physical address */
+ u32 fdss; /* Offset 178 FFS Display Size */
+ u32 stat; /* Offset 182 State Indicator */
+ u64 rvda; /* Offset 186 (Igd opregion offset 0x3BAh) Physical address of Raw VBT data */
+ u32 rvds; /* Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data */
+ u8 reserved[58]; /* Offset 198 Reserved */
} __attribute__((packed)) opregion_mailbox3_t;
#define IGD_BACKLIGHT_BRIGHTNESS 0xff
@@ -111,9 +164,16 @@ typedef struct {
/* mailbox 4: vbt */
typedef struct {
- u8 gvd1[7168];
+ u8 gvd1[6*KiB];
} __attribute__((packed)) opregion_vbt_t;
+/* Mailbox 5: BIOS to Driver Notification Extension */
+typedef struct {
+ u32 phed; /* Offset 7168 Panel Header */
+ u8 bddc[256]; /* Offset 7172 Panel EDID */
+ u8 reserved[764]; /* Offset 7428 764 bytes */
+} __attribute__((packed)) opregion_mailbox5_t;
+
/* IGD OpRegion */
typedef struct {
opregion_header_t header;
@@ -121,6 +181,8 @@ typedef struct {
opregion_mailbox2_t mailbox2;
opregion_mailbox3_t mailbox3;
opregion_vbt_t vbt;
+ opregion_mailbox5_t mailbox5;
+
} __attribute__((packed)) igd_opregion_t;
/* Intel Video BIOS (Option ROM) */
diff --git a/src/soc/intel/common/opregion.c b/src/soc/intel/common/opregion.c
index 44c27fb8fa..fe85d3d263 100644
--- a/src/soc/intel/common/opregion.c
+++ b/src/soc/intel/common/opregion.c
@@ -15,6 +15,7 @@
#include <console/console.h>
#include <string.h>
+#include <cbmem.h>
#include "gma.h"
#include "opregion.h"
@@ -24,6 +25,7 @@ int init_igd_opregion(igd_opregion_t *opregion)
{
struct region_device vbt_rdev;
optionrom_vbt_t *vbt;
+ optionrom_vbt_t *ext_vbt;
if (locate_vbt(&vbt_rdev) == CB_ERR) {
printk(BIOS_ERR, "VBT not found\n");
@@ -43,8 +45,22 @@ int init_igd_opregion(igd_opregion_t *opregion)
sizeof(opregion->header.signature));
memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild,
ARRAY_SIZE(vbt->coreblock_biosbuild));
- memcpy(opregion->vbt.gvd1, vbt, MIN(vbt->hdr_vbt_size,
- sizeof(opregion->vbt.gvd1)));
+ /* Extended VBT support */
+ if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) {
+ ext_vbt = cbmem_add(CBMEM_ID_EXT_VBT, vbt->hdr_vbt_size);
+
+ if (ext_vbt == NULL) {
+ printk(BIOS_ERR, "Unable to add Ext VBT to cbmem!\n");
+ return 0;
+ }
+
+ memcpy(ext_vbt, vbt, vbt->hdr_vbt_size);
+ opregion->mailbox3.rvda = (uintptr_t)ext_vbt;
+ opregion->mailbox3.rvds = vbt->hdr_vbt_size;
+ } else {
+ /* Raw VBT size which can fit in gvd1 */
+ memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size);
+ }
/* 8KiB */
opregion->header.size = sizeof(igd_opregion_t) / KiB;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 07:54:37 +0000