diff options
21 files changed, 95 insertions, 93 deletions
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 08f61c2a9a..7a6333b93f 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -17,15 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ - +#ifndef __ROMCC__ #include <stdint.h> #include <console/console.h> -#include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/amd/microcode.h> -#include <cpu/x86/cache.h> +#endif +#ifndef __PRE_RAM__ +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> #endif struct microcode { diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index cce44d7869..3a86be296f 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -30,7 +30,6 @@ #define SET_FIDVID_CORE0_ONLY 0 #endif -void update_microcode(u32 cpu_deviceid); static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); void cpuSetAMDMSR(void); diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index d0511a75ce..ef6d8e084b 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -37,8 +37,6 @@ #include <cpu/amd/multicore.h> #include <cpu/amd/model_10xxx_msr.h> -extern device_t get_node_pci(u32 nodeid, u32 fn); - #define MCI_STATUS 0x401 msr_t rdmsr_amd(u32 index) diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index 85b1aa84bf..b6c2c22945 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -23,7 +23,9 @@ #include <device/device.h> #include <device/pci.h> #include <string.h> +#endif +#ifndef __ROMCC__ #include <cpu/amd/microcode.h> #endif diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h index ece4528cf7..9f46015241 100644 --- a/src/include/cpu/amd/microcode.h +++ b/src/include/cpu/amd/microcode.h @@ -2,6 +2,7 @@ #define CPU_AMD_MICORCODE_H void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id); +void update_microcode(u32 processor_rev_id); void model_fxx_update_microcode(unsigned cpu_deviceid); #endif /* CPU_AMD_MICROCODE_H */ diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 1f5366912d..17a0fd606f 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -93,6 +93,8 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -100,8 +102,6 @@ static int spd_read_byte(u32 device, u32 address) #include "southbridge/amd/sb700/sb700_early_setup.c" //#include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" #define RC00 0 #define RC01 1 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 316e257dc1..b571d37c40 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -115,6 +115,8 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -122,8 +124,6 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 4a3e9f4c95..0d2f80fcf8 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -118,6 +118,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -140,8 +142,6 @@ static void sio_setup(void) } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index a60a4a610a..a763414a4e 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -107,6 +107,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -137,8 +139,6 @@ static void sio_setup(void) } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index e17614bbf1..1b2686dbda 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -111,6 +111,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -141,8 +143,6 @@ static void sio_setup(void) } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 128f3b3f49..5f6d2a7691 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -113,10 +113,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - - #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -144,8 +144,6 @@ static void sio_setup(void) } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 1fbef83236..81dec8858d 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1084,6 +1084,10 @@ struct sys_info { } __attribute__((packed)); +#ifndef __PRE_RAM__ +device_t get_node_pci(u32 nodeid, u32 fn); +#endif + #if CONFIG_AMDMCT == 0 #ifdef __PRE_RAM__ diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index a7007357c0..cab2ec86d9 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -22,6 +22,7 @@ */ #include "amdfam10_pci.c" +#include <delay.h> static inline void print_debug_addr(const char *str, void *val) { @@ -89,8 +90,6 @@ static inline void print_pci_devices_on_bus(u32 busn) } } - - static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) { int i; @@ -111,10 +110,12 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) } print_debug("\n"); } + static void dump_pci_device(u32 dev) { dump_pci_device_range(dev, 0, 4096); } + static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, u32 size) { @@ -136,13 +137,13 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, } print_debug("\n"); } + static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg) { dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54); dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz // dump_pci_device_index_wait_range(dev, index_reg, 0x200, 0x08); //DIMM2 // dump_pci_device_index_wait_range(dev, index_reg, 0x300, 0x08); //DIMM3 - } static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length) @@ -165,7 +166,6 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l print_debug("\n"); } - static inline void dump_pci_devices(void) { device_t dev; @@ -191,7 +191,6 @@ static inline void dump_pci_devices(void) } } - static inline void dump_pci_devices_on_bus(u32 busn) { device_t dev; diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 6c36d00f7b..0a298727b7 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -157,7 +157,7 @@ u32 mctGetLogicalCPUID(u32 Node) } -void raminit_amdmct(struct sys_info *sysinfo) +static void raminit_amdmct(struct sys_info *sysinfo) { struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index be02ab3d3b..038ecdcb9d 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -123,7 +123,7 @@ * @param[out] u8 results = the number of nodes in the graph * --------------------------------------------------------------------------------------- */ -u8 graphHowManyNodes(u8 *graph) +static u8 graphHowManyNodes(u8 *graph) { return graph[0]; } @@ -144,7 +144,7 @@ u8 graphHowManyNodes(u8 *graph) * @param[out] BOOL results = true if nodeA connects to nodeB false if not * --------------------------------------------------------------------------------------- */ -BOOL graphIsAdjacent(u8 *graph, u8 nodeA, u8 nodeB) +static BOOL graphIsAdjacent(u8 *graph, u8 nodeA, u8 nodeB) { u8 size = graph[0]; ASSERT(size <= MAX_NODES); @@ -170,7 +170,7 @@ BOOL graphIsAdjacent(u8 *graph, u8 nodeA, u8 nodeB) * @param[out] u8 results = The response route node * --------------------------------------------------------------------------------------- */ -u8 graphGetRsp(u8 *graph, u8 nodeA, u8 nodeB) +static u8 graphGetRsp(u8 *graph, u8 nodeA, u8 nodeB) { u8 size = graph[0]; ASSERT(size <= MAX_NODES); @@ -196,7 +196,7 @@ u8 graphGetRsp(u8 *graph, u8 nodeA, u8 nodeB) * @param[out] u8 results = The request route node * --------------------------------------------------------------------------------------- */ -u8 graphGetReq(u8 *graph, u8 nodeA, u8 nodeB) +static u8 graphGetReq(u8 *graph, u8 nodeA, u8 nodeB) { u8 size = graph[0]; ASSERT(size <= MAX_NODES); @@ -219,7 +219,7 @@ u8 graphGetReq(u8 *graph, u8 nodeA, u8 nodeB) * OU u8 results = the broadcast routes for nodeA from nodeB * --------------------------------------------------------------------------------------- */ -u8 graphGetBc(u8 *graph, u8 nodeA, u8 nodeB) +static u8 graphGetBc(u8 *graph, u8 nodeA, u8 nodeB) { u8 size = graph[0]; ASSERT(size <= MAX_NODES); @@ -248,7 +248,7 @@ u8 graphGetBc(u8 *graph, u8 nodeA, u8 nodeB) * @param[in] sMainData* pDat = our global state, port config info * --------------------------------------------------------------------------------------- */ -void routeFromBSP(u8 targetNode, u8 actualTarget, sMainData *pDat) +static void routeFromBSP(u8 targetNode, u8 actualTarget, sMainData *pDat) { u8 predecessorNode, predecessorLink, currentPair; @@ -287,7 +287,7 @@ void routeFromBSP(u8 targetNode, u8 actualTarget, sMainData *pDat) * @param[out] u8 results = the link on source which connects to target * --------------------------------------------------------------------------------------- */ -u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) +static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) { u8 targetlink = INVALID_LINK; u8 k; @@ -326,7 +326,7 @@ u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) * @param[in] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void htDiscoveryFloodFill(sMainData *pDat) +static void htDiscoveryFloodFill(sMainData *pDat) { u8 currentNode = 0; u8 currentLink; @@ -595,7 +595,7 @@ void htDiscoveryFloodFill(sMainData *pDat) * @param[out] BOOL results = the graphs are (or are not) isomorphic * --------------------------------------------------------------------------------------- */ -BOOL isoMorph(u8 i, sMainData *pDat) +static BOOL isoMorph(u8 i, sMainData *pDat) { u8 j, k; u8 nodecnt; @@ -669,7 +669,7 @@ BOOL isoMorph(u8 i, sMainData *pDat) * @param[out] degree matrix, permutation * --------------------------------------------------------------------------------------- */ -void lookupComputeAndLoadRoutingTables(sMainData *pDat) +static void lookupComputeAndLoadRoutingTables(sMainData *pDat) { u8 **pTopologyList; u8 *pSelected; @@ -810,7 +810,7 @@ void lookupComputeAndLoadRoutingTables(sMainData *pDat) * @param[in] sMainData* pDat = our global state, number of nodes discovered. * --------------------------------------------------------------------------------------- */ -void finializeCoherentInit(sMainData *pDat) +static void finializeCoherentInit(sMainData *pDat) { u8 curNode; @@ -843,7 +843,7 @@ void finializeCoherentInit(sMainData *pDat) * @param[in] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void coherentInit(sMainData *pDat) +static void coherentInit(sMainData *pDat) { u8 i, j; @@ -891,7 +891,7 @@ void coherentInit(sMainData *pDat) * @param[in] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void processLink(u8 node, u8 link, sMainData *pDat) +static void processLink(u8 node, u8 link, sMainData *pDat) { u8 secBus, subBus; u32 currentBUID; @@ -1184,7 +1184,7 @@ void processLink(u8 node, u8 link, sMainData *pDat) * @param[in] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void ncInit(sMainData *pDat) +static void ncInit(sMainData *pDat) { u8 node, link; u8 compatLink; @@ -1228,7 +1228,7 @@ void ncInit(sMainData *pDat) * @param[in,out] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void regangLinks(sMainData *pDat) +static void regangLinks(sMainData *pDat) { #ifndef HT_BUILD_NC_ONLY u8 i, j; @@ -1317,7 +1317,7 @@ void regangLinks(sMainData *pDat) * @param[in,out] sMainData* pDat = our global state, port list data * --------------------------------------------------------------------------------------- */ -void selectOptimalWidthAndFrequency(sMainData *pDat) +static void selectOptimalWidthAndFrequency(sMainData *pDat) { u8 i, j; u32 temp; @@ -1452,7 +1452,7 @@ void selectOptimalWidthAndFrequency(sMainData *pDat) * @param[in,out] sMainData* pDat = our global state, link state and port list * --------------------------------------------------------------------------------------- */ -void hammerSublinkFixup(sMainData *pDat) +static void hammerSublinkFixup(sMainData *pDat) { #ifndef HT_BUILD_NC_ONLY u8 i, j, k; @@ -1589,7 +1589,7 @@ void hammerSublinkFixup(sMainData *pDat) * @param[in] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void linkOptimization(sMainData *pDat) +static void linkOptimization(sMainData *pDat) { pDat->nb->gatherLinkData(pDat, pDat->nb); regangLinks(pDat); @@ -1611,7 +1611,7 @@ void linkOptimization(sMainData *pDat) * @param[in] sMainData* pDat = our global state, port list data * --------------------------------------------------------------------------------------- */ -void trafficDistribution(sMainData *pDat) +static void trafficDistribution(sMainData *pDat) { #ifndef HT_BUILD_NC_ONLY u32 links01, links10; @@ -1654,7 +1654,7 @@ void trafficDistribution(sMainData *pDat) * @param[in] sMainData* pDat = our global state, port list data * --------------------------------------------------------------------------------------- */ -void tuning(sMainData *pDat) +static void tuning(sMainData *pDat) { u8 i; @@ -1692,7 +1692,7 @@ void tuning(sMainData *pDat) * @param[out] result BOOL = true if check is ok, false if it failed * --------------------------------------------------------------------------------------- */ -BOOL isSanityCheckOk(void) +static BOOL isSanityCheckOk(void) { uint64 qValue; diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index a2b4076d22..f02ce44f80 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -80,7 +80,7 @@ static u32 get_nodes(void) /** * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) */ -void AMD_CB_EventNotify (u8 evtClass, u16 event, u8 *pEventData0) +static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) { u8 i; @@ -114,9 +114,9 @@ void AMD_CB_EventNotify (u8 evtClass, u16 event, u8 *pEventData0) * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u16 link, u8 **List) +static BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, u8 **List) { - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + static u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; /* If the BUID was adjusted in early_ht we need to do the manual override */ if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); @@ -148,7 +148,7 @@ void getAmdTopolist(u8 ***p) * AMD HT init coreboot wrapper * */ -void amd_ht_init(struct sys_info *sysinfo) +static void amd_ht_init(struct sys_info *sysinfo) { AMD_HTBLOCK ht_wrapper = { diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index ec767fa27c..ef7e2af92a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -177,7 +177,7 @@ static const u8 Table_Comp_Rise_Slew_15x[] = {7, 7, 3, 2, 0xFF}; static const u8 Table_Comp_Fall_Slew_20x[] = {7, 5, 3, 2, 0xFF}; static const u8 Table_Comp_Fall_Slew_15x[] = {7, 7, 5, 3, 0xFF}; -void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, +static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { /* @@ -3565,7 +3565,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, u8 Node; u32 i; struct DCTStatStruc *pDCTstat; - u16 start, stop; + u32 start, stop; u8 *p; u16 host_serv1, host_serv2; @@ -3582,12 +3582,12 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, p = (u8 *) pDCTstat; start = 0; - stop = ((u16) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); + stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); for (i = start; i < stop ; i++) { p[i] = 0; } - start = ((u16) &((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); + start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); stop = sizeof(struct DCTStatStruc); for (i = start; i < stop; i++) { p[i] = 0; @@ -3617,7 +3617,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, } -void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, +static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 *dqs_pos) { // FIXME: Skip for Ax diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index 8cbeef11df..3e36dfe4cc 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -150,7 +150,7 @@ static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num) } -u32 read32_fs(u32 addr_lo) +static u32 read32_fs(u32 addr_lo) { u32 value; __asm__ volatile ( @@ -162,7 +162,7 @@ u32 read32_fs(u32 addr_lo) } -u8 read8_fs(u32 addr_lo) +static u8 read8_fs(u32 addr_lo) { u8 byte; __asm__ volatile ( @@ -312,7 +312,7 @@ static void ReadMaxRdLat1CLTestPattern_D(u32 addr) } -void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) +static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) { SetUpperFSbase(addr); @@ -351,7 +351,7 @@ static void FlushMaxRdLatTestPattern_D(u32 addr) } -u32 stream_to_int(u8 *p) +static u32 stream_to_int(u8 const *p) { int i; u32 val; @@ -369,19 +369,19 @@ u32 stream_to_int(u8 *p) } -void oemSet_NB32(u32 addr, u32 val, u8 *valid) +static void oemSet_NB32(u32 addr, u32 val, u8 *valid) { } -u32 oemGet_NB32(u32 addr, u8 *valid) +static u32 oemGet_NB32(u32 addr, u8 *valid) { *valid = 0; return 0xffffffff; } -u8 oemNodePresent_D(u8 Node, u8 *ret) +static u8 oemNodePresent_D(u8 Node, u8 *ret) { *ret = 0; return 0; diff --git a/src/northbridge/amd/amdmct/mct/mct_fd.c b/src/northbridge/amd/amdmct/mct/mct_fd.c index c54d6ef90b..168d9957d9 100644 --- a/src/northbridge/amd/amdmct/mct/mct_fd.c +++ b/src/northbridge/amd/amdmct/mct/mct_fd.c @@ -19,7 +19,7 @@ -u8 amd_FD_support(void) +static u8 amd_FD_support(void) { return 1; } diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index c18e8e58ba..9cb2856edb 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -104,7 +104,7 @@ static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, u8 *CMDmode) { - u8 *p; + u8 const *p; *AddrTmgCTL = 0; *ODC_CTL = 0; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 54ee28f8d5..6dfeb214d0 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -19,7 +19,7 @@ /* Call-backs */ #include <delay.h> -u16 mctGet_NVbits(u8 index) +static u16 mctGet_NVbits(u8 index) { u16 val = 0; @@ -223,106 +223,106 @@ u16 mctGet_NVbits(u8 index) } -void mctHookAfterDIMMpre(void) +static void mctHookAfterDIMMpre(void) { } -void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) +static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) { pDCTstat->PresetmaxFreq = 400; } -void mctAdjustAutoCycTmg(void) +static void mctAdjustAutoCycTmg(void) { } -void mctAdjustAutoCycTmg_D(void) +static void mctAdjustAutoCycTmg_D(void) { } -void mctHookAfterAutoCycTmg(void) +static void mctHookAfterAutoCycTmg(void) { } -void mctGetCS_ExcludeMap(void) +static void mctGetCS_ExcludeMap(void) { } -void mctHookAfterAutoCfg(void) +static void mctHookAfterAutoCfg(void) { } -void mctHookAfterPSCfg(void) +static void mctHookAfterPSCfg(void) { } -void mctHookAfterHTMap(void) +static void mctHookAfterHTMap(void) { } -void mctHookAfterCPU(void) +static void mctHookAfterCPU(void) { } -void mctSaveDQSSigTmg_D(void) +static void mctSaveDQSSigTmg_D(void) { } -void mctGetDQSSigTmg_D(void) +static void mctGetDQSSigTmg_D(void) { } -void mctHookBeforeECC(void) +static void mctHookBeforeECC(void) { } -void mctHookAfterECC(void) +static void mctHookAfterECC(void) { } -void mctInitMemGPIOs_A(void) +static void mctInitMemGPIOs_A(void) { } -void mctInitMemGPIOs_A_D(void) +static void mctInitMemGPIOs_A_D(void) { } -void mctNodeIDDebugPort_D(void) +static void mctNodeIDDebugPort_D(void) { } -void mctWarmReset(void) +static void mctWarmReset(void) { } -void mctWarmReset_D(void) +static void mctWarmReset_D(void) { } -void mctHookBeforeDramInit(void) +static void mctHookBeforeDramInit(void) { } -void mctHookAfterDramInit(void) +static void mctHookAfterDramInit(void) { } @@ -330,7 +330,7 @@ static void coreDelay (void); /* Erratum 350 */ -void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) +static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u8 u8Channel; u8 u8Receiver; @@ -392,23 +392,23 @@ void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) } -void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) +static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2)) { vErrata350(pMCTstat, pDCTstatA); } } -void mctHookAfterAnyTraining(void) +static void mctHookAfterAnyTraining(void) { } -u32 mctGetLogicalCPUID_D(u8 node) +static u32 mctGetLogicalCPUID_D(u8 node) { return mctGetLogicalCPUID(node); } -u8 mctSetNodeBoundary_D(void) +static u8 mctSetNodeBoundary_D(void) { return 0; } |