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-rw-r--r--src/cpu/amd/geode_lx/Makefile.inc4
-rw-r--r--src/cpu/amd/geode_lx/cpureginit.c10
-rw-r--r--src/cpu/amd/geode_lx/msrinit.c6
-rw-r--r--src/cpu/amd/geode_lx/syspreinit.c3
-rw-r--r--src/include/cpu/amd/lxdef.h4
-rw-r--r--src/mainboard/pcengines/alix1c/romstage.c17
-rw-r--r--src/mainboard/pcengines/alix2d/romstage.c10
-rw-r--r--src/northbridge/amd/lx/Makefile.inc1
-rw-r--r--src/northbridge/amd/lx/northbridge.h6
-rw-r--r--src/northbridge/amd/lx/pll_reset.c5
10 files changed, 40 insertions, 26 deletions
diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc
index 22a3fda49c..99be61e374 100644
--- a/src/cpu/amd/geode_lx/Makefile.inc
+++ b/src/cpu/amd/geode_lx/Makefile.inc
@@ -3,6 +3,10 @@ subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
+romstage-y += cpureginit.c
+romstage-y += syspreinit.c
+romstage-y += msrinit.c
+
ramstage-y += geode_lx_init.c
ramstage-y += cpubug.c
diff --git a/src/cpu/amd/geode_lx/cpureginit.c b/src/cpu/amd/geode_lx/cpureginit.c
index eac8fa7455..a61501e58e 100644
--- a/src/cpu/amd/geode_lx/cpureginit.c
+++ b/src/cpu/amd/geode_lx/cpureginit.c
@@ -16,9 +16,13 @@
* GNU General Public License for more details.
*/
-/* SetDelayControl */
-#include "cpu/x86/msr.h"
-
+#include <stdint.h>
+#include <spd.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/lxdef.h>
+#include <northbridge/amd/lx/raminit.h>
+#include <northbridge/amd/lx/northbridge.h>
/**
* Delay Control Settings table from AMD (MCP 0x4C00000F).
diff --git a/src/cpu/amd/geode_lx/msrinit.c b/src/cpu/amd/geode_lx/msrinit.c
index e6e6247cad..827bb61f3a 100644
--- a/src/cpu/amd/geode_lx/msrinit.c
+++ b/src/cpu/amd/geode_lx/msrinit.c
@@ -14,7 +14,9 @@
*/
#include <stdlib.h>
-#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/x86/msr.h>
+#include <northbridge/amd/lx/northbridge.h>
static const msrinit_t msr_table[] =
{
@@ -50,7 +52,7 @@ static const msrinit_t msr_table[] =
{MSR_GLIU1_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
};
-static void msr_init(void)
+void lx_msr_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(msr_table); i++)
diff --git a/src/cpu/amd/geode_lx/syspreinit.c b/src/cpu/amd/geode_lx/syspreinit.c
index de6e141a94..801aea91b0 100644
--- a/src/cpu/amd/geode_lx/syspreinit.c
+++ b/src/cpu/amd/geode_lx/syspreinit.c
@@ -16,6 +16,9 @@
* GNU General Public License for more details.
*/
+#include <arch/io.h>
+#include <cpu/amd/lxdef.h>
+
/**
* StartTimer1
*
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index c47717aed3..7daa294340 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -644,6 +644,10 @@
#define DELAY_LOWER_STATUS_MASK 0x7C0
#if !defined(__ASSEMBLER__)
+
+#include <stdint.h>
+#include <arch/cpu.h>
+
#if defined(__PRE_RAM__)
void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated);
void SystemPreInit(void);
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index 4c06ada723..8fe2dc09d5 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -25,14 +25,14 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include <cpu/amd/car.h>
-#include <southbridge/amd/cs5536/cs5536.h>
#include <northbridge/amd/lx/raminit.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
+#include <northbridge/amd/lx/northbridge.h>
+#include <southbridge/amd/cs5536/cs5536.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
/* The part is a Hynix hy5du121622ctp-d43.
*
* HY 5D U 12 16 2 2 C <blank> T <blank> P D43
@@ -88,11 +88,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
return spdbytes[address];
}
-#include "northbridge/amd/lx/pll_reset.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
@@ -100,7 +95,7 @@ void asmlinkage mainboard_romstage_entry(unsigned long bist)
};
SystemPreInit();
- msr_init();
+ lx_msr_init();
cs5536_early_setup();
@@ -114,7 +109,7 @@ void asmlinkage mainboard_romstage_entry(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset();
+ lx_pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index e653c9f03e..da3913d2a4 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -27,6 +27,7 @@
#include <cpu/amd/car.h>
#include <southbridge/amd/cs5536/cs5536.h>
#include <northbridge/amd/lx/raminit.h>
+#include <northbridge/amd/lx/northbridge.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -85,11 +86,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
return spdbytes[address];
}
-#include "northbridge/amd/lx/pll_reset.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
/** Early mainboard specific GPIO setup. */
static void mb_gpio_init(void)
{
@@ -122,7 +118,7 @@ void asmlinkage mainboard_romstage_entry(unsigned long bist)
};
SystemPreInit();
- msr_init();
+ lx_msr_init();
cs5536_early_setup();
@@ -136,7 +132,7 @@ void asmlinkage mainboard_romstage_entry(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pll_reset();
+ lx_pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
diff --git a/src/northbridge/amd/lx/Makefile.inc b/src/northbridge/amd/lx/Makefile.inc
index 190c0598e4..e36139ff6d 100644
--- a/src/northbridge/amd/lx/Makefile.inc
+++ b/src/northbridge/amd/lx/Makefile.inc
@@ -6,5 +6,6 @@ ramstage-y += grphinit.c
romstage-y += raminit.c
romstage-y += generic_sdram.c
+romstage-y += pll_reset.c
endif
diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h
index 9a4ff29664..51c2c14e75 100644
--- a/src/northbridge/amd/lx/northbridge.h
+++ b/src/northbridge/amd/lx/northbridge.h
@@ -16,8 +16,6 @@
#ifndef NORTHBRIDGE_AMD_LX_H
#define NORTHBRIDGE_AMD_LX_H
-#include <cpu/amd/lxdef.h>
-
/* northbridge.c */
int sizeram(void);
@@ -26,4 +24,8 @@ void northbridge_init_early(void);
/* pll_reset.c */
unsigned int GeodeLinkSpeed(void);
+void lx_pll_reset(void);
+
+void lx_msr_init(void);
+
#endif
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index d98a8ea1b6..cb332ead12 100644
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -14,9 +14,12 @@
* GNU General Public License for more details.
*/
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/lxdef.h>
#include "northbridge.h"
-static void pll_reset(void)
+void lx_pll_reset(void)
{
msr_t msrGlcpSysRstpll;