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-rw-r--r--src/arch/armv7/tables.c7
-rw-r--r--src/arch/x86/boot/cbmem.c5
-rw-r--r--src/arch/x86/boot/tables.c13
-rw-r--r--src/include/cbmem.h1
-rw-r--r--src/lib/cbmem.c10
-rw-r--r--src/mainboard/google/pit/mainboard.c17
-rw-r--r--src/mainboard/google/snow/mainboard.c17
7 files changed, 44 insertions, 26 deletions
diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c
index 0fc7399c13..0f174d30ff 100644
--- a/src/arch/armv7/tables.c
+++ b/src/arch/armv7/tables.c
@@ -29,13 +29,6 @@
#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
-/*
- * TODO: "High" tables are a convention used on x86. Maybe we can
- * clean up that naming at some point.
- */
-uint64_t high_tables_base = 0;
-uint64_t high_tables_size;
-
void cbmem_arch_init(void)
{
}
diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c
index 3f738be07b..6ec005d183 100644
--- a/src/arch/x86/boot/cbmem.c
+++ b/src/arch/x86/boot/cbmem.c
@@ -25,9 +25,6 @@
*/
void set_top_of_ram(uint64_t ramtop)
{
- high_tables_base = ramtop - HIGH_MEMORY_SIZE;
- high_tables_size = HIGH_MEMORY_SIZE;
- printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n",
- high_tables_base, high_tables_size);
+ cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE);
}
#endif
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c
index 67d7911fe2..31d0fc7a4a 100644
--- a/src/arch/x86/boot/tables.c
+++ b/src/arch/x86/boot/tables.c
@@ -32,8 +32,6 @@
#include <lib.h>
#include <smbios.h>
-uint64_t high_tables_base = 0;
-uint64_t high_tables_size;
void cbmem_arch_init(void)
{
@@ -227,9 +225,18 @@ struct lb_memory *write_tables(void)
if (high_table_pointer) {
unsigned long new_high_table_pointer;
+ /* FIXME: The high_table_base parameter is not reference when tables are high,
+ * or high_table_pointer >1 MB.
+ */
+#if CONFIG_DYNAMIC_CBMEM
+ u64 fixme_high_tables_base = 0;
+#else
+ u64 fixme_high_tables_base = high_tables_base;
+#endif
+
/* Also put a forwarder entry into 0-4K */
new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end,
- high_tables_base, high_table_pointer);
+ fixme_high_tables_base, high_table_pointer);
if (new_high_table_pointer > (high_table_pointer +
MAX_COREBOOT_TABLE_SIZE))
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 00d74d6d9c..3d047630f4 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -137,6 +137,7 @@ void cbmem_add_lb_mem(struct lb_memory *mem);
#ifndef __PRE_RAM__
extern uint64_t high_tables_base, high_tables_size;
void set_top_of_ram(uint64_t ramtop);
+void cbmem_late_set_table(uint64_t base, uint64_t size);
void set_cbmem_toc(struct cbmem_entry *);
#endif
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 9e2ce0df84..206fdbf887 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -42,6 +42,8 @@ struct cbmem_entry {
} __attribute__((packed));
#ifndef __PRE_RAM__
+uint64_t high_tables_base = 0;
+uint64_t high_tables_size = 0;
static struct cbmem_entry *bss_cbmem_toc;
struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
@@ -60,7 +62,15 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n");
return NULL;
}
+#endif
+#if !defined(__PRE_RAM__)
+void cbmem_late_set_table(uint64_t base, uint64_t size)
+{
+ printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", base, base+size-1, __FUNCTION__);
+ high_tables_base = base;
+ high_tables_size = size;
+}
#endif
/**
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 54ea042bd5..7dd8388596 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -221,17 +221,22 @@ static void mainboard_init(device_t dev)
// gpio_info();
}
+static void setup_cbmem(void)
+{
+ u64 size = CONFIG_COREBOOT_TABLES_SIZE;
+ u64 base = CONFIG_SYS_SDRAM_BASE +
+ ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
+ CONFIG_COREBOOT_TABLES_SIZE;
+ cbmem_late_set_table(base, size);
+ cbmem_init(base, size);
+}
+
static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
/* set up coreboot tables */
- /* FIXME: this should happen somewhere else */
- high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
- high_tables_base = CONFIG_SYS_SDRAM_BASE +
- ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
- CONFIG_COREBOOT_TABLES_SIZE;
- cbmem_init(high_tables_base, high_tables_size);
+ setup_cbmem();
/* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index 5aedac9646..8805be5fb7 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -262,17 +262,22 @@ static void mainboard_init(device_t dev)
// gpio_info();
}
+static void setup_cbmem(void)
+{
+ u64 size = CONFIG_COREBOOT_TABLES_SIZE;
+ u64 base = CONFIG_SYS_SDRAM_BASE +
+ ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
+ CONFIG_COREBOOT_TABLES_SIZE;
+ cbmem_late_set_table(base, size);
+ cbmem_init(base, size);
+}
+
static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
/* set up coreboot tables */
- /* FIXME: this should happen somewhere else */
- high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
- high_tables_base = CONFIG_SYS_SDRAM_BASE +
- ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
- CONFIG_COREBOOT_TABLES_SIZE;
- cbmem_init(high_tables_base, high_tables_size);
+ setup_cbmem();
/* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */