diff options
| -rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 3 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 3 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/smmrelocate.c | 3 | ||||
| -rw-r--r-- | src/cpu/intel/hyperthreading/intel_sibling.c | 13 | ||||
| -rw-r--r-- | src/cpu/intel/model_1067x/model_1067x_init.c | 6 | ||||
| -rw-r--r-- | src/cpu/intel/slot_1/l2_cache.c | 6 | ||||
| -rw-r--r-- | src/cpu/intel/smm/gen1/smmrelocate.c | 6 | ||||
| -rw-r--r-- | src/cpu/intel/speedstep/acpi.c | 3 |
8 files changed, 15 insertions, 28 deletions
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 89869e4418..0f6be3988f 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -792,9 +792,8 @@ static const struct mp_ops mp_ops = { void bsp_init_and_start_aps(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) { + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); - } } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index a1a6c317fa..c6765c757c 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -248,9 +248,8 @@ void romstage_common(const struct romstage_params *params) romstage_handoff_init(wake_from_s3); post_code(0x3f); - if (IS_ENABLED(CONFIG_LPC_TPM)) { + if (IS_ENABLED(CONFIG_LPC_TPM)) init_tpm(wake_from_s3); - } } asmlinkage void romstage_after_car(void) diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 3ec009ec37..e7a9ee1620 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -330,9 +330,8 @@ void smm_initialize(void) */ smm_initiate_relocation(); - if (smm_reloc_params.smm_save_state_in_msrs) { + if (smm_reloc_params.smm_save_state_in_msrs) printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); - } } /* The default SMM entry can happen in parallel or serially. If the diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 640d9b37f5..57aa00c007 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -63,14 +63,13 @@ void intel_sibling_init(struct device *cpu) } result = cpuid(1); /* Is hyperthreading supported */ - if (!(result.edx & (1 << 28))) { + if (!(result.edx & (1 << 28))) return; - } + /* See how many sibling cpus we have */ siblings = (result.ebx >> 16) & 0xff; - if (siblings < 1) { + if (siblings < 1) siblings = 1; - } printk(BIOS_DEBUG, "CPU: %u %d siblings\n", cpu->path.apic.apic_id, @@ -78,9 +77,8 @@ void intel_sibling_init(struct device *cpu) /* See if I am a sibling cpu */ if (cpu->path.apic.apic_id & (siblings - 1)) { - if (disable_siblings) { + if (disable_siblings) cpu->enabled = 0; - } return; } @@ -98,9 +96,8 @@ void intel_sibling_init(struct device *cpu) */ new = alloc_find_dev(cpu->bus, &cpu_path); - if (!new) { + if (!new) continue; - } printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", cpu->path.apic.apic_id, diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index d4bf0f4063..9b7536de57 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -66,9 +66,8 @@ static void configure_c_states(const int quad) msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 8); - if (quad) { + if (quad) msr.lo = (msr.lo & ~(7 << 0)) | (4 << 0); - } if (c5) { msr.lo &= ~(1 << 13); msr.lo &= ~(7 << 0); @@ -203,9 +202,8 @@ static void configure_misc(const int eist, const int tm2, const int emttm) msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ /* Enable C2E */ - if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) { + if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) msr.lo |= (1 << 26); - } /* Enable C4E */ if (((sub_cstates >> (4 * 4)) & 0xf) >= 2) { diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index 1415a0da4f..b7b9719747 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -221,9 +221,8 @@ int signal_l2(u32 address, u32 data_high, u32 data_low, int way, u8 command) /* Write data to BBL_CR_D{0..3} */ msr.lo = data_low; msr.hi = data_high; - for (i = BBL_CR_D0; i <= BBL_CR_D3; i++) { + for (i = BBL_CR_D0; i <= BBL_CR_D3; i++) wrmsr(i, msr); - } /* Put the command and way into BBL_CR_CTL */ msr = rdmsr(BBL_CR_CTL); @@ -669,8 +668,7 @@ int p6_configure_l2_cache(void) printk(BIOS_DEBUG, "write_l2(4, %x)\n", v); a = read_l2(4); - if (a >= 0) - { + if (a >= 0) { a &= 0xfffc; a |= v; a = write_l2(4, a); diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 2cbe6013cc..c3596d29a7 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -157,9 +157,8 @@ static int install_relocation_handler(int *apic_id_map, int num_cpus, if (smm_setup_relocation_handler(&smm_params)) return -1; int i; - for (i = 0; i < num_cpus; i++) { + for (i = 0; i < num_cpus; i++) smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i]; - } return 0; } @@ -201,9 +200,8 @@ static int install_permanent_handler(int *apic_id_map, int num_cpus, relo_params->smram_size, &smm_params)) return -1; int i; - for (i = 0; i < num_cpus; i++) { + for (i = 0; i < num_cpus; i++) smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i]; - } return 0; } diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index b6e29adde9..f801307627 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -33,9 +33,8 @@ static int determine_total_number_of_cores(void) (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { continue; } - if (!cpu->enabled) { + if (!cpu->enabled) continue; - } count++; } return count; |