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-rw-r--r--src/arch/x86/lib/c_start.S9
-rw-r--r--src/include/bootstate.h2
-rw-r--r--src/lib/hardwaremain.c12
-rw-r--r--src/mainboard/emulation/qemu-armv7/ramstage.c6
-rw-r--r--src/mainboard/google/snow/ramstage.c8
-rw-r--r--src/northbridge/via/vx800/examples/chipset_init.c2
6 files changed, 10 insertions, 29 deletions
diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S
index 32af0ccdf9..99a4d92d4b 100644
--- a/src/arch/x86/lib/c_start.S
+++ b/src/arch/x86/lib/c_start.S
@@ -49,12 +49,6 @@ _start:
pushl $0
pushl $0
- /* push the boot_complete flag */
- pushl %ebp
-
- /* Save the stack location */
- movl %esp, %ebp
-
/* Initialize the Interrupt Descriptor table */
leal _idt, %edi
leal vec0, %ebx
@@ -80,9 +74,6 @@ _start:
*/
post_code(POST_PRE_HARDWAREMAIN) /* post fe */
- /* Restore the stack location */
- movl %ebp, %esp
-
#if CONFIG_GDB_WAIT
call gdb_stub_breakpoint
#endif
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 0370c36067..40822a79e2 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -165,7 +165,7 @@ void boot_state_current_block(void);
void boot_state_current_unblock(void);
/* Entry into the boot state machine. */
-void hardwaremain(int boot_complete);
+void hardwaremain(void);
/* In order to schedule boot state callbacks at compile-time specify the
* entries in an array using the BOOT_STATE_INIT_ENTRIES and
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 13aa512a51..99b4a069b4 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -444,7 +444,7 @@ static void boot_state_schedule_static_entries(void)
}
}
-void hardwaremain(int boot_complete)
+void hardwaremain(void)
{
timestamp_stash(TS_START_RAMSTAGE);
post_code(POST_ENTRY_RAMSTAGE);
@@ -454,17 +454,11 @@ void hardwaremain(int boot_complete)
post_code(POST_CONSOLE_READY);
- printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n",
- coreboot_version, coreboot_extra_version, coreboot_build,
- (boot_complete)?"rebooting":"booting");
+ printk(BIOS_NOTICE, "coreboot-%s%s %s booting...\n",
+ coreboot_version, coreboot_extra_version, coreboot_build);
post_code(POST_CONSOLE_BOOT_MSG);
- /* If we have already booted attempt a hard reboot */
- if (boot_complete) {
- hard_reset();
- }
-
/* Schedule the static boot state entries. */
boot_state_schedule_static_entries();
diff --git a/src/mainboard/emulation/qemu-armv7/ramstage.c b/src/mainboard/emulation/qemu-armv7/ramstage.c
index 24d0d7ff8f..5fce9fa68c 100644
--- a/src/mainboard/emulation/qemu-armv7/ramstage.c
+++ b/src/mainboard/emulation/qemu-armv7/ramstage.c
@@ -15,10 +15,8 @@
#include <console/console.h>
-void hardwaremain(int boot_complete);
+void hardwaremain(void);
void main(void)
{
- console_init();
- printk(BIOS_INFO, "hello from ramstage\n");
- hardwaremain(0);
+ hardwaremain();
}
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index 09b51a79fa..72f830dec6 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -77,12 +77,10 @@ void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
}
-void hardwaremain(int boot_complete);
+void hardwaremain(void);
void main(void)
{
- console_init();
- printk(BIOS_INFO,
- "hello from ramstage; now with deluxe exception handling.\n");
+ /* FIXME this should be moved elsewhere. We don't want ramstage.c */
/* set up coreboot tables */
high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
@@ -114,7 +112,7 @@ void main(void)
power_enable_xclkout();
- hardwaremain(0);
+ hardwaremain();
}
/* TODO: transplanted DP stuff, clean up once we have something that works */
diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c
index 1e06d478b6..d9b85e4b98 100644
--- a/src/northbridge/via/vx800/examples/chipset_init.c
+++ b/src/northbridge/via/vx800/examples/chipset_init.c
@@ -604,7 +604,7 @@ void init_VIA_chipset(void)
* In the dev_enumerate() phase,
*/
-void hardwaremain(int boot_complete)
+void hardwaremain(void)
{
struct lb_memory *lb_mem;
#if CONFIG_HAVE_ACPI_RESUME