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-rw-r--r--src/soc/intel/braswell/chip.h4
-rw-r--r--src/soc/intel/braswell/include/soc/lpc.h4
-rw-r--r--src/soc/intel/braswell/southcluster.c40
3 files changed, 38 insertions, 10 deletions
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 9fde4d12a6..4afaf44417 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -3,6 +3,7 @@
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2019 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,6 +25,7 @@
#include <stdint.h>
#include <fsp/util.h>
+#include <intelblocks/lpc_lib.h>
#include <soc/pci_devs.h>
#define SVID_CONFIG1 1
@@ -54,6 +56,8 @@ struct soc_intel_braswell_config {
uint8_t enable_xdp_tap;
uint8_t clkreq_enable;
+ enum serirq_mode serirq_mode;
+
/* Disable SLP_X stretching after SUS power well loss. */
int disable_slp_x_stretch_sus_fail;
diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h
index 7b1e3424e9..1a56f9e8c1 100644
--- a/src/soc/intel/braswell/include/soc/lpc.h
+++ b/src/soc/intel/braswell/include/soc/lpc.h
@@ -31,6 +31,10 @@
#define UART_CONT 0x80
#define RCBA 0xf0
+/* iLB Memory Mapped IO */
+#define ILB_OIC 0x60
+#define SIRQEN (1 << 12)
+
/* Memory Mapped IO in LPC bridge */
#define SCNT 0x10
#define SCNT_MODE (1 << 7) /* When cleared, SERIRQ is in quiet mode */
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index e79cb128a5..000790d9a6 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -28,6 +28,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <intelblocks/lpc_lib.h>
#include <pc80/isa-dma.h>
#include <pc80/i8254.h>
#include <pc80/i8259.h>
@@ -41,17 +42,23 @@
#include <soc/spi.h>
#include <spi-generic.h>
#include <stdint.h>
-#include <reg_script.h>
-static const struct reg_script ops[] = {
- REG_MMIO_RMW32(ILB_BASE_ADDRESS + SCNT,
- ~SCNT_MODE, 0), /* put LPC SERIRQ in Quiet Mode */
- REG_SCRIPT_END
-};
-
-static void enable_serirq_quiet_mode(void)
+static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode)
{
- reg_script_run(ops);
+ u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
+
+ switch (mode) {
+ case SERIRQ_CONTINUOUS:
+ break;
+ case SERIRQ_OFF:
+ write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) &
+ ~SIRQEN);
+ break;
+ case SERIRQ_QUIET:
+ default:
+ write8(ilb_base + SCNT, read8(ilb_base + SCNT) & ~SCNT_MODE);
+ break;
+ }
}
static inline void
@@ -85,6 +92,15 @@ static void sc_add_mmio_resources(struct device *dev)
#define LPC_DEFAULT_IO_RANGE_LOWER 0
#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
+static void sc_enable_serial_irqs(struct device *dev)
+{
+ u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
+
+ printk(BIOS_SPEW, "Enable serial irq\n");
+ write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) | SIRQEN);
+ write8(ilb_base + SCNT, read8(ilb_base + SCNT) | SCNT_MODE);
+}
+
/*
* Write PCI config space IRQ assignments. PCI devices have the INT_LINE
* (0x3C) and INT_PIN (0x3D) registers which report interrupt routing
@@ -285,6 +301,8 @@ static void sc_init(struct device *dev)
isa_dma_init();
+ sc_enable_serial_irqs(dev);
+
/* Set up the PIRQ PIC routing based on static config. */
for (i = 0; i < NUM_PIRQS; i++)
write8((void *)(pr_base + i*sizeof(ir->pic[i])),
@@ -320,6 +338,9 @@ static void sc_init(struct device *dev)
/* Initialize i8254 timers */
setup_i8254();
+
+ sc_set_serial_irqs_mode(dev, config->serirq_mode);
+
}
/*
@@ -630,7 +651,6 @@ static void finalize_chipset(void *unused)
write32(spi + LVSCC, cfg.lvscc | VCL);
}
spi_init();
- enable_serirq_quiet_mode();
printk(BIOS_DEBUG, "Finalizing SMM.\n");
outb(APM_CNT_FINALIZE, APM_CNT);