summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/cpu/dmp/dmp_post_code.h33
-rw-r--r--src/mainboard/dmp/vortex86ex/romstage.c10
-rw-r--r--src/southbridge/dmp/vortex86ex/southbridge.c15
3 files changed, 41 insertions, 17 deletions
diff --git a/src/cpu/dmp/dmp_post_code.h b/src/cpu/dmp/dmp_post_code.h
new file mode 100644
index 0000000000..6658ce8b02
--- /dev/null
+++ b/src/cpu/dmp/dmp_post_code.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef DMP_POST_CODE_H
+#define DMP_POST_CODE_H
+
+/* DMP Vortex86EX specific POST codes */
+
+#define POST_DMP_KBD_FW_UPLOAD 0x06
+#define POST_DMP_KBD_CHK_READY 0x07
+#define POST_DMP_KBD_IS_READY 0x08
+#define POST_DMP_KBD_FW_VERIFY_ERR 0x82
+#define POST_DMP_ID_ERR 0x85
+#define POST_DMP_DRAM_TEST_ERR 0x86
+#define POST_DMP_DRAM_SIZING_ERR 0x77
+
+#endif /* DMP_POST_CODE_H*/
diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c
index 72fbde08e5..b08d621e75 100644
--- a/src/mainboard/dmp/vortex86ex/romstage.c
+++ b/src/mainboard/dmp/vortex86ex/romstage.c
@@ -27,6 +27,7 @@
#include "northbridge/dmp/vortex86ex/northbridge.h"
#include "southbridge/dmp/vortex86ex/southbridge.h"
#include "northbridge/dmp/vortex86ex/raminit.c"
+#include "cpu/dmp/dmp_post_code.h"
#define DMP_CPUID_SX 0x31504d44
#define DMP_CPUID_DX 0x32504d44
@@ -35,11 +36,6 @@
#define DMP_CPUID_MX_PLUS 0x35504d44
#define DMP_CPUID_EX 0x37504d44
-/* Post codes */
-#define POST_DMP_ID_ERR 0x85
-#define POST_DRAM_TEST_ERR 0x86
-#define POST_DRAM_SIZING_ERR 0x77
-
static u32 get_dmp_id(void)
{
return pci_read_config32(NB, NB_REG_CID);
@@ -273,7 +269,7 @@ static void test_dram_stability(void)
}
}
if (v != -1) {
- post_code(POST_DRAM_TEST_ERR);
+ post_code(POST_DMP_DRAM_TEST_ERR);
print_emerg("DRAM stablility test error!\nADDR = ");
print_emerg_hex32(v);
print_emerg(", WRITE = ");
@@ -342,7 +338,7 @@ static void main(unsigned long bist)
reg_nb_f1_cc &= ~(1 << 4);
pci_write_config8(NB1, 0xcc, reg_nb_f1_cc);
if (detect_ddr3_dram_size()) {
- post_code(POST_DRAM_SIZING_ERR);
+ post_code(POST_DMP_DRAM_SIZING_ERR);
die("DRAM sizing error!\n");
}
/* Reset enhance read push write to default(enable) */
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index ddb99b8241..61c484f9ae 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -28,6 +28,7 @@
#include "arch/io.h"
#include "chip.h"
#include "southbridge.h"
+#include "cpu/dmp/dmp_post_code.h"
/* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */
static const unsigned char irq_to_int_routing[16] = {
@@ -89,12 +90,6 @@ static const unsigned char irq_to_int_routing[16] = {
#define LPT_PDMAS 0
#define LPT_DREQS 0
-/* Post codes */
-#define POST_KBD_FW_UPLOAD 0x06
-#define POST_KBD_CHK_READY 0x07
-#define POST_KBD_IS_READY 0x08
-#define POST_KBD_FW_VERIFY_FAILURE 0x82
-
static u8 get_pci_dev_func(device_t dev)
{
return PCI_FUNC(dev->path.pci.devfn);
@@ -102,7 +97,7 @@ static u8 get_pci_dev_func(device_t dev)
static void verify_dmp_keyboard_error(void)
{
- post_code(POST_KBD_FW_VERIFY_FAILURE);
+ post_code(POST_DMP_KBD_FW_VERIFY_ERR);
die("Internal keyboard firmware verify error!\n");
}
@@ -112,7 +107,7 @@ static void upload_dmp_keyboard_firmware(struct device *dev)
u32 fwptr;
// enable firmware uploading function by set bit 10.
- post_code(POST_KBD_FW_UPLOAD);
+ post_code(POST_DMP_KBD_FW_UPLOAD);
reg_sb_c0 = pci_read_config32(dev, SB_REG_IPFCR);
pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 | 0x400);
@@ -145,10 +140,10 @@ static void kbc_wait_system_flag(void)
/* wait keyboard controller ready by checking system flag
* (status port bit 2).
*/
- post_code(POST_KBD_CHK_READY);
+ post_code(POST_DMP_KBD_CHK_READY);
while ((inb(0x64) & 0x4) == 0) {
}
- post_code(POST_KBD_IS_READY);
+ post_code(POST_DMP_KBD_IS_READY);
}
static void pci_routing_fixup(struct device *dev)