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-rw-r--r--src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl64
-rw-r--r--src/mainboard/google/butterfly/acpi_tables.c18
-rw-r--r--src/mainboard/google/butterfly/devicetree.cb9
-rw-r--r--src/mainboard/google/butterfly/romstage.c42
-rw-r--r--src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl68
-rw-r--r--src/mainboard/google/link/acpi_tables.c18
-rw-r--r--src/mainboard/google/link/devicetree.cb9
-rw-r--r--src/mainboard/google/link/romstage.c39
-rw-r--r--src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl68
-rw-r--r--src/mainboard/google/parrot/acpi_tables.c18
-rw-r--r--src/mainboard/google/parrot/devicetree.cb9
-rw-r--r--src/mainboard/google/parrot/romstage.c43
-rw-r--r--src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl72
-rw-r--r--src/mainboard/google/stout/acpi_tables.c18
-rw-r--r--src/mainboard/google/stout/devicetree.cb9
-rw-r--r--src/mainboard/google/stout/romstage.c43
-rw-r--r--src/mainboard/intel/cougar_canyon2/devicetree.cb9
-rw-r--r--src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl68
-rw-r--r--src/mainboard/intel/emeraldlake2/acpi_tables.c18
-rw-r--r--src/mainboard/intel/emeraldlake2/devicetree.cb9
-rw-r--r--src/mainboard/intel/emeraldlake2/romstage.c38
-rw-r--r--src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl87
-rw-r--r--src/mainboard/kontron/ktqm77/acpi_tables.c18
-rw-r--r--src/mainboard/kontron/ktqm77/devicetree.cb9
-rw-r--r--src/mainboard/kontron/ktqm77/romstage.c58
-rw-r--r--src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl64
-rw-r--r--src/mainboard/lenovo/t520/acpi_tables.c18
-rw-r--r--src/mainboard/lenovo/t520/devicetree.cb9
-rw-r--r--src/mainboard/lenovo/t520/romstage.c42
-rw-r--r--src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl64
-rw-r--r--src/mainboard/lenovo/t530/acpi_tables.c18
-rw-r--r--src/mainboard/lenovo/t530/devicetree.cb9
-rw-r--r--src/mainboard/lenovo/t530/romstage.c42
-rw-r--r--src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl86
-rw-r--r--src/mainboard/lenovo/x201/acpi_tables.c36
-rw-r--r--src/mainboard/lenovo/x201/devicetree.cb9
-rw-r--r--src/mainboard/lenovo/x201/romstage.c40
-rw-r--r--src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl64
-rw-r--r--src/mainboard/lenovo/x220/acpi_tables.c18
-rw-r--r--src/mainboard/lenovo/x220/devicetree.cb9
-rw-r--r--src/mainboard/lenovo/x220/romstage.c42
-rw-r--r--src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl64
-rw-r--r--src/mainboard/lenovo/x230/acpi_tables.c18
-rw-r--r--src/mainboard/lenovo/x230/devicetree.cb9
-rw-r--r--src/mainboard/lenovo/x230/romstage.c42
-rw-r--r--src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl86
-rw-r--r--src/mainboard/packardbell/ms2290/acpi_tables.c36
-rw-r--r--src/mainboard/packardbell/ms2290/devicetree.cb9
-rw-r--r--src/mainboard/packardbell/ms2290/romstage.c41
-rw-r--r--src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl68
-rw-r--r--src/mainboard/samsung/lumpy/acpi_tables.c18
-rw-r--r--src/mainboard/samsung/lumpy/devicetree.cb9
-rw-r--r--src/mainboard/samsung/lumpy/romstage.c36
-rw-r--r--src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl68
-rw-r--r--src/mainboard/samsung/stumpy/acpi_tables.c18
-rw-r--r--src/mainboard/samsung/stumpy/devicetree.cb9
-rw-r--r--src/mainboard/samsung/stumpy/romstage.c38
-rw-r--r--src/northbridge/intel/nehalem/acpi/hostbridge.asl3
-rw-r--r--src/northbridge/intel/sandybridge/acpi/hostbridge.asl3
-rw-r--r--src/northbridge/intel/sandybridge/romstage_native.c1
-rw-r--r--src/southbridge/intel/bd82x6x/Makefile.inc3
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/irq.asl72
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/pch.asl2
-rw-r--r--src/southbridge/intel/bd82x6x/chip.h13
-rw-r--r--src/southbridge/intel/bd82x6x/early_rcba.c69
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c43
-rw-r--r--src/southbridge/intel/bd82x6x/madt.c45
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h1
-rw-r--r--src/southbridge/intel/ibexpeak/Makefile.inc2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c43
-rw-r--r--src/southbridge/intel/ibexpeak/madt.c68
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h1
72 files changed, 319 insertions, 2050 deletions
diff --git a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index 6c1c6952b8..0000000000
--- a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
- Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
- Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
- Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
- Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- })
- }
-}
diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c
index dcaf3845be..cabc052b78 100644
--- a/src/mainboard/google/butterfly/acpi_tables.c
+++ b/src/mainboard/google/butterfly/acpi_tables.c
@@ -75,24 +75,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index daafeffb53..ed0d8d1887 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -39,15 +39,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 6b7613a85b..80c0742985 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -62,47 +62,7 @@ static void rcba_config(void)
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP WLAN INTA -> PIRQB
- * D28IP_P2IP ETH0 INTB -> PIRQF
- * D28IP_P3IP SDCARD INTC -> PIRQD
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQF
- * D31IP_SIP SATA INTA -> PIRQB (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- *
- * Trackpad interrupt is edge triggered and cannot be shared.
- * TRACKPAD -> PIRQG
-
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
- (INTC << D28IP_P3IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
+ southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
diff --git a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index a4267bb253..0000000000
--- a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 19 },
- Package() { 0x001cffff, 1, 0, 20 },
- Package() { 0x001cffff, 2, 0, 17 },
- Package() { 0x001cffff, 3, 0, 18 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 21 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 17 },
- Package() { 0x001fffff, 1, 0, 23 },
- Package() { 0x001fffff, 2, 0, 16 },
- Package() { 0x001fffff, 3, 0, 18 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
- })
- }
-}
diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c
index 14baad2d45..d1d4fcba18 100644
--- a/src/mainboard/google/link/acpi_tables.c
+++ b/src/mainboard/google/link/acpi_tables.c
@@ -83,24 +83,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->lids = 1;
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index 15aa432e64..5333dfc2c3 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -42,15 +42,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 8236e2062d..f90d7e7728 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -78,44 +78,7 @@ static void rcba_config(void)
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P3IP WLAN INTA -> PIRQB
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQF
- * D31IP_SIP SATA INTA -> PIRQF (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- *
- * TRACKPAD -> PIRQE (Edge Triggered)
- * TOUCHSCREEN -> PIRQG (Edge Triggered)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P3IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
+ southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
diff --git a/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index a4267bb253..0000000000
--- a/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 19 },
- Package() { 0x001cffff, 1, 0, 20 },
- Package() { 0x001cffff, 2, 0, 17 },
- Package() { 0x001cffff, 3, 0, 18 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 21 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 17 },
- Package() { 0x001fffff, 1, 0, 23 },
- Package() { 0x001fffff, 2, 0, 16 },
- Package() { 0x001fffff, 3, 0, 18 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
- })
- }
-}
diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c
index e4e1797731..0041c98fd4 100644
--- a/src/mainboard/google/parrot/acpi_tables.c
+++ b/src/mainboard/google/parrot/acpi_tables.c
@@ -74,24 +74,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->lids = 1;
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index 2da7a5333b..a4baafd9ca 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -41,15 +41,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x8b"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index ce42b4126e..c25b419389 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -62,48 +62,7 @@ static void rcba_config(void)
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P2IP WLAN INTA -> PIRQB
- * D28IP_P3IP ETH0 INTC -> PIRQD
- * D29IP_E1P EHCI1 INTA -> PIRQE
- * D26IP_E2P EHCI2 INTA -> PIRQE
- * D31IP_SIP SATA INTA -> PIRQF (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQG
- * D31IP_TTIP THRT INTC -> PIRQH
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- *
- * Trackpad DVT PIRQA (16)
- * Trackpad DVT PIRQE (20)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
- (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
- (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) |
- (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
+ southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
diff --git a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index cf3d82a181..0000000000
--- a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, 0, 19 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 19 },
- Package() { 0x001cffff, 1, 0, 20 },
- Package() { 0x001cffff, 2, 0, 17 },
- Package() { 0x001cffff, 3, 0, 18 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 21 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 17 },
- Package() { 0x001fffff, 1, 0, 23 },
- Package() { 0x001fffff, 2, 0, 16 },
- Package() { 0x001fffff, 3, 0, 18 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
- })
- }
-}
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
index 504ae64e3e..23c47f96f5 100644
--- a/src/mainboard/google/stout/acpi_tables.c
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -80,24 +80,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->xhci = XHCI_MODE;
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 97e2c09a0f..4ac89f629f 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -40,15 +40,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 728d74d842..6290e03165 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -68,48 +68,7 @@ static void rcba_config(void)
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D20IP_XHCI XHCI INTA -> PIRQD (MSI)
- * D26IP_E2P EHCI #2 INTA -> PIRQF
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- * D28IP_P2IP WLAN INTA -> PIRQD
- * D28IP_P3IP Card Reader INTB -> PIRQE
- * D28IP_P6IP LAN INTC -> PIRQB
- * D29IP_E1P EHCI #1 INTA -> PIRQD
- * D31IP_SIP SATA INTA -> PIRQB (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
- (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
- (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) |
- (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
- RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC);
- DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
+ southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb
index 42b1535f5b..c386853a1c 100644
--- a/src/mainboard/intel/cougar_canyon2/devicetree.cb
+++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb
@@ -32,15 +32,6 @@ chip northbridge/intel/fsp_sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/fsp_bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
register "sata_port_map" = "0x3f"
register "c2_latency" = "1"
diff --git a/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl b/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index a57f9f1f55..0000000000
--- a/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },
- Package() { 0x001cffff, 1, 0, 18 },
- Package() { 0x001cffff, 2, 0, 19 },
- Package() { 0x001cffff, 3, 0, 20 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 20 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 21 },
- Package() { 0x001fffff, 1, 0, 22 },
- Package() { 0x001fffff, 2, 0, 23 },
- Package() { 0x001fffff, 3, 0, 16 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- })
- }
-}
diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c
index 3d95586869..f17e1f4819 100644
--- a/src/mainboard/intel/emeraldlake2/acpi_tables.c
+++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c
@@ -92,24 +92,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index 75643f4a5b..e5a8ea0edd 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -32,15 +32,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 220b1d731d..d50093e08d 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -73,43 +73,7 @@ static void rcba_config(void)
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP WLAN INTA -> PIRQB
- * D28IP_P4IP ETH0 INTB -> PIRQC
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQE
- * D31IP_SIP SATA INTA -> PIRQF (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQG
- * D31IP_TTIP THRT INTC -> PIRQH
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
- (INTB << D28IP_P4IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
+ southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
diff --git a/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index ceb40be356..0000000000
--- a/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 secunet Security Networks AG
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Ivybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // LPC devices 0:1f.x
- // D31IP_TTIP THRT INTC -> PIRQC
- Package() { 0x001fffff, 2, 0, 18 },// D31IP_SMIP SMBUS INTC -> PIRQC
- Package() { 0x001fffff, 1, 0, 19 },// D31IP_SIP SATA INTB -> PIRQD (MSI)
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 23 },// D29IP_E1P EHCI1 INTA -> PIRQH
- // PCIe Root Ports 0:1c.x
- // D28IP_P8IP Slot? INTD -> PIRQD
- Package() { 0x001cffff, 3, 0, 19 },// D28IP_P4IP ETH2 INTD -> PIRQD (MSI)
- // D28IP_P7IP PCIEx1 INTC -> PIRQC
- Package() { 0x001cffff, 2, 0, 18 },// D28IP_P3IP ETH1 INTC -> PIRQC (MSI)
- // D28IP_P6IP 1394 INTB -> PIRQB (MSI)
- Package() { 0x001cffff, 1, 0, 17 },// D28IP_P2IP Slot? INTB -> PIRQB
- // D28IP_P5IP GbEPHY INTA -> PIRQA
- Package() { 0x001cffff, 0, 0, 16 },// D28IP_P1IP Slot? INTA -> PIRQA
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },// D27IP_ZIP HDA INTA -> PIRQG (MSI)
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 16 },// D26IP_E2P EHCI2 INTA -> PIRQA
- // ETH0 0:19.0
- Package() { 0x0019ffff, 0, 0, 20 },// D25IP_LIP ETH0 INTA -> PIRQE (MSI)
- // xHCI 0:14.0
- Package() { 0x0014ffff, 0, 0, 16 },// D20IP_XHCIIP xHCI INTA -> PIRQA (MSI)
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
- // PCIe PEG x16 0:1.0
- Package() { 0x0001ffff, 3, 0, 19 },// PEGx16 INTD -> PIRQD
- Package() { 0x0001ffff, 2, 0, 18 },// PEGx16 INTC -> PIRQC
- Package() { 0x0001ffff, 1, 0, 17 },// PEGx16 INTB -> PIRQB
- Package() { 0x0001ffff, 0, 0, 16 },// PEGx16 INTA -> PIRQA
- })
- } Else {
- Return (Package() {
- // LPC devices 0:1f.x
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // ETH0 0:19.0
- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
- // xHCI 0:14.0
- Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe PEG x16 0:1.0
- Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- })
- }
-}
diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c
index 0d90403bf0..d2d70e9fca 100644
--- a/src/mainboard/kontron/ktqm77/acpi_tables.c
+++ b/src/mainboard/kontron/ktqm77/acpi_tables.c
@@ -63,24 +63,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
acpi_update_thermal_table(gnvs);
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb
index fb180577a9..855fd5c7f6 100644
--- a/src/mainboard/kontron/ktqm77/devicetree.cb
+++ b/src/mainboard/kontron/ktqm77/devicetree.cb
@@ -27,15 +27,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8b"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x8b"
- register "pirqf_routing" = "0x8b"
- register "pirqg_routing" = "0x8b"
- register "pirqh_routing" = "0x8b"
-
# Enable all SATA ports 0-5
register "sata_port_map" = "0x3f"
# Set max SATA speed to 6.0 Gb/s (should be the default, anyway)
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 401314cd8d..bfe7715826 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -59,63 +59,7 @@ static void rcba_config(void)
{
u32 reg32;
- /*
- * D31IP_TTIP THRT INTC -> PIRQC
- * D31IP_SIP2 SATA2 NOINT
- * D31IP_SMIP SMBUS INTC -> PIRQC
- * D31IP_SIP SATA INTB -> PIRQD (MSI)
- * D29IP_E1P EHCI1 INTA -> PIRQH
- * D28IP_P8IP Slot? INTD -> PIRQD
- * D28IP_P7IP PCIEx1 INTC -> PIRQC
- * D28IP_P6IP 1394 INTB -> PIRQB (MSI)
- * D28IP_P5IP GbEPHY INTA -> PIRQA
- * D28IP_P4IP ETH2 INTD -> PIRQD (MSI)
- * D28IP_P3IP ETH1 INTC -> PIRQC (MSI)
- * D28IP_P2IP Slot? INTB -> PIRQB
- * D28IP_P1IP Slot? INTA -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- * D26IP_E2P EHCI2 INTA -> PIRQA
- * D25IP_LIP ETH0 INTA -> PIRQE (MSI)
- * D22IP_KTIP MEI NOINT
- * D22IP_IDERIP MEI NOINT
- * D22IP_MEI2IP MEI NOINT
- * D22IP_MEI1IP MEI NOINT
- * D20IP_XHCIIP XHCI INTA -> PIRQA (MSI)
- * GFX INTA -> PIRQA (MSI)
- * PEGx16 INTA -> PIRQA
- * INTB -> PIRQB
- * INTC -> PIRQC
- * INTD -> PIRQD
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTC << D31IP_SMIP) | (INTB << D31IP_SIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
- (INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) |
- (INTA << D28IP_P5IP) | (INTB << D28IP_P6IP) |
- (INTC << D28IP_P7IP) | (INTD << D28IP_P8IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (INTA << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
- RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA);
- DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC);
- DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD);
- DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH);
- DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB);
- DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
+ southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
diff --git a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index b4b81a2270..0000000000
--- a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },// D28IP_P2IP WLAN INTA -> PIRQB
- Package() { 0x001cffff, 1, 0, 21 },// D28IP_P4IP EXC INTB -> PIRQF
- Package() { 0x001cffff, 2, 0, 19 },// D28IP_P5IP SDCARD INTC -> PIRQD
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
- Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
- Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- })
- }
-}
diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c
index 26a459dfaf..15b9d9a4e4 100644
--- a/src/mainboard/lenovo/t520/acpi_tables.c
+++ b/src/mainboard/lenovo/t520/acpi_tables.c
@@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
acpi_update_thermal_table(gnvs);
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 065261a8c0..d2a4d6b9b7 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -44,15 +44,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 83be0c7f86..f7866a86ad 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -60,48 +60,6 @@ void pch_enable_lpc(void)
void rcba_config(void)
{
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P2IP WLAN INTA -> PIRQB
- * D28IP_P4IP EXC INTB -> PIRQF
- * D28IP_P5IP SDCARD INTC -> PIRQD
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQF
- * D31IP_SIP SATA INTA -> PIRQB (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- *
- * Trackpad interrupt is edge triggered and cannot be shared.
- * TRACKPAD -> PIRQG
-
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P2IP) | (INTB << D28IP_P4IP) |
- (INTC << D28IP_P5IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
-
/* Disable unused devices (board specific) */
RCBA32(FD) = 0x1ee51fe3;
RCBA32(BUC) = 0;
diff --git a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index 6c1c6952b8..0000000000
--- a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
- Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
- Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
- Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
- Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- })
- }
-}
diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c
index 26a459dfaf..15b9d9a4e4 100644
--- a/src/mainboard/lenovo/t530/acpi_tables.c
+++ b/src/mainboard/lenovo/t530/acpi_tables.c
@@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
acpi_update_thermal_table(gnvs);
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index ec3913c5f6..c44f927747 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -44,15 +44,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 115f83bdbc..0a49ed05c3 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -47,48 +47,6 @@ void pch_enable_lpc(void)
void rcba_config(void)
{
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP WLAN INTA -> PIRQB
- * D28IP_P2IP ETH0 INTB -> PIRQF
- * D28IP_P3IP SDCARD INTC -> PIRQD
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQF
- * D31IP_SIP SATA INTA -> PIRQB (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- *
- * Trackpad interrupt is edge triggered and cannot be shared.
- * TRACKPAD -> PIRQG
-
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
- (INTC << D28IP_P3IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
-
/* Disable unused devices (board specific) */
RCBA32(FD) = 0x17f81fe3;
RCBA32(BUC) = 0;
diff --git a/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl b/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl
deleted file mode 100644
index 3e9e1b3ca7..0000000000
--- a/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Vladimir Serbinenko
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing.
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- Package() { 0x0001ffff, 0, 0, 0x10 },
- Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
- Package() { 0x0003ffff, 0, 0, 0x10 },
- Package() { 0x0016ffff, 0, 0, 0x10 }, // ME
- Package() { 0x0016ffff, 1, 0, 0x11 }, // ME
- Package() { 0x0016ffff, 2, 0, 0x12 }, // ME
- Package() { 0x0016ffff, 3, 0, 0x13 }, // ME
- Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet
- Package() { 0x001affff, 0, 0, 0x14 }, // USB
- Package() { 0x001affff, 1, 0, 0x15 }, // USB
- Package() { 0x001affff, 2, 0, 0x16 }, // USB
- Package() { 0x001affff, 3, 0, 0x17 }, // USB
- Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
- Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge
- Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge
- Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge
- Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge
- Package() { 0x001dffff, 0, 0, 0x10 }, // USB
- Package() { 0x001dffff, 1, 0, 0x11 }, // USB
- Package() { 0x001dffff, 2, 0, 0x12 }, // USB
- Package() { 0x001dffff, 3, 0, 0x13 }, // USB
- Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
- Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
- Package() { 0x001fffff, 2, 0, 0x11 }, // SATA
- Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS
- })
- } Else {
- Return (Package() {
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
- Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME
- Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME
- Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME
- Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME
- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB
- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB
- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB
- Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB
- Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus
- })
- }
-}
diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c
index b8979f495a..85eabc7d1f 100644
--- a/src/mainboard/lenovo/x201/acpi_tables.c
+++ b/src/mainboard/lenovo/x201/acpi_tables.c
@@ -48,42 +48,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs)
gnvs->did[4] = 0x00000005;
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 1, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2,
- MP_IRQ_POLARITY_DEFAULT |
- MP_IRQ_TRIGGER_DEFAULT);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9,
- MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_LEVEL);
-
- /* LAPIC_NMI */
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 0,
- MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 1, MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 2, MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 3, MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
/* Not implemented */
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index 614245cba9..117c25c891 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -93,15 +93,6 @@ chip northbridge/intel/nehalem
subsystemid 0x17aa 0x215a
end
chip southbridge/intel/ibexpeak
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 2c3dfd1bcc..e58f5f6d5e 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -75,41 +75,9 @@ static void pch_enable_lpc(void)
static void rcba_config(void)
{
+ southbridge_configure_default_intmap();
+
static const u32 rcba_dump3[] = {
- /* 30fc */ 0x00000000,
- /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321,
- /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002,
- /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000,
- /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654,
- /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210,
- /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000,
- /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,
/* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,
/* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -179,8 +147,8 @@ static void rcba_config(void)
};
unsigned i;
for (i = 0; i < sizeof(rcba_dump3) / 4; i++) {
- RCBA32(4 * i + 0x30fc) = rcba_dump3[i];
- (void)RCBA32(4 * i + 0x30fc);
+ RCBA32(4 * i + 0x3310) = rcba_dump3[i];
+ (void)RCBA32(4 * i + 0x3310);
}
}
diff --git a/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index 6c1c6952b8..0000000000
--- a/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
- Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
- Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
- Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
- Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- })
- }
-}
diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c
index 26a459dfaf..15b9d9a4e4 100644
--- a/src/mainboard/lenovo/x220/acpi_tables.c
+++ b/src/mainboard/lenovo/x220/acpi_tables.c
@@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
acpi_update_thermal_table(gnvs);
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index c1bea43e99..982e30bb09 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -48,15 +48,6 @@ chip northbridge/intel/sandybridge
end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index ba48fac574..d9c8aa04e1 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -57,48 +57,6 @@ void pch_enable_lpc(void)
void rcba_config(void)
{
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP WLAN INTA -> PIRQB
- * D28IP_P2IP ETH0 INTB -> PIRQF
- * D28IP_P3IP SDCARD INTC -> PIRQD
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQF
- * D31IP_SIP SATA INTA -> PIRQB (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- *
- * Trackpad interrupt is edge triggered and cannot be shared.
- * TRACKPAD -> PIRQG
-
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
- (INTC << D28IP_P3IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
-
/* Disable unused devices (board specific) */
RCBA32(FD) = 0x1fe41fe3;
RCBA32(BUC) = 0;
diff --git a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index 6c1c6952b8..0000000000
--- a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
- Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
- Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
- Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
- Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- })
- }
-}
diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c
index 26a459dfaf..15b9d9a4e4 100644
--- a/src/mainboard/lenovo/x230/acpi_tables.c
+++ b/src/mainboard/lenovo/x230/acpi_tables.c
@@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
acpi_update_thermal_table(gnvs);
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index c44a2b7a1a..5130410e90 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -48,15 +48,6 @@ chip northbridge/intel/sandybridge
end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 2c39741770..0bb137e732 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -60,48 +60,6 @@ void pch_enable_lpc(void)
void rcba_config(void)
{
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP WLAN INTA -> PIRQB
- * D28IP_P2IP ETH0 INTB -> PIRQF
- * D28IP_P3IP SDCARD INTC -> PIRQD
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQF
- * D31IP_SIP SATA INTA -> PIRQB (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- *
- * Trackpad interrupt is edge triggered and cannot be shared.
- * TRACKPAD -> PIRQG
-
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
- (INTC << D28IP_P3IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
-
/* Disable unused devices (board specific) */
RCBA32(FD) = 0x17f81fe3;
RCBA32(BUC) = 0;
diff --git a/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl b/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl
deleted file mode 100644
index 1f782c8c89..0000000000
--- a/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Vladimir Serbinenko
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing.
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- Package() { 0x0001ffff, 0, 0, 0x10 },
- Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
- Package() { 0x0003ffff, 0, 0, 0x10 },
- Package() { 0x0016ffff, 0, 0, 0x10 }, // ME
- Package() { 0x0016ffff, 1, 0, 0x11 }, // ME
- Package() { 0x0016ffff, 2, 0, 0x12 }, // ME
- Package() { 0x0016ffff, 3, 0, 0x13 }, // ME
- Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet
- Package() { 0x001affff, 0, 0, 0x14 }, // USB
- Package() { 0x001affff, 1, 0, 0x15 }, // USB
- Package() { 0x001affff, 2, 0, 0x16 }, // USB
- Package() { 0x001affff, 3, 0, 0x17 }, // USB
- Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
- Package() { 0x001cffff, 0, 0, 0x10 }, // PCI bridge
- Package() { 0x001cffff, 1, 0, 0x11 }, // PCI bridge
- Package() { 0x001cffff, 2, 0, 0x12 }, // PCI bridge
- Package() { 0x001cffff, 3, 0, 0x13 }, // PCI bridge
- Package() { 0x001dffff, 0, 0, 0x10 }, // USB
- Package() { 0x001dffff, 1, 0, 0x11 }, // USB
- Package() { 0x001dffff, 2, 0, 0x12 }, // USB
- Package() { 0x001dffff, 3, 0, 0x13 }, // USB
- Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
- Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
- Package() { 0x001fffff, 2, 0, 0x11 }, // SATA
- Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS
- })
- } Else {
- Return (Package() {
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
- Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME
- Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME
- Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME
- Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME
- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB
- Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB
- Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB
- Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB
- Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // PCI
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // PCI
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // PCI
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // PCI
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus
- })
- }
-}
diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c
index b8979f495a..85eabc7d1f 100644
--- a/src/mainboard/packardbell/ms2290/acpi_tables.c
+++ b/src/mainboard/packardbell/ms2290/acpi_tables.c
@@ -48,42 +48,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs)
gnvs->did[4] = 0x00000005;
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 1, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2,
- MP_IRQ_POLARITY_DEFAULT |
- MP_IRQ_TRIGGER_DEFAULT);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9,
- MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_LEVEL);
-
- /* LAPIC_NMI */
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 0,
- MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 1, MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 2, MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, 3, MP_IRQ_POLARITY_HIGH |
- MP_IRQ_TRIGGER_EDGE, 0x01);
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
/* Not implemented */
diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb
index 19f6c9c207..2f4bce11dc 100644
--- a/src/mainboard/packardbell/ms2290/devicetree.cb
+++ b/src/mainboard/packardbell/ms2290/devicetree.cb
@@ -54,15 +54,6 @@ chip northbridge/intel/nehalem
subsystemid 0x1025 0x0379
end
chip southbridge/intel/ibexpeak
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index d33a9baf71..ca96c87f5d 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -70,41 +70,9 @@ static void pch_enable_lpc(void)
static void rcba_config(void)
{
+ southbridge_configure_default_intmap();
+
static const u32 rcba_dump3[] = {
- /* 30fc */ 0x00000000,
- /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321,
- /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002,
- /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000,
- /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654,
- /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210,
- /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000,
- /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,
/* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,
/* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -173,9 +141,10 @@ static void rcba_config(void)
/* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000,
};
unsigned i;
+
for (i = 0; i < sizeof(rcba_dump3) / 4; i++) {
- RCBA32(4 * i + 0x30fc) = rcba_dump3[i];
- (void)RCBA32(4 * i + 0x30fc);
+ RCBA32(4 * i + 0x3310) = rcba_dump3[i];
+ (void)RCBA32(4 * i + 0x3310);
}
}
diff --git a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index aff2351625..0000000000
--- a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },
- Package() { 0x001cffff, 1, 0, 18 },
- Package() { 0x001cffff, 2, 0, 19 },
- Package() { 0x001cffff, 3, 0, 16 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 17 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 16 },
- Package() { 0x001fffff, 1, 0, 22 },
- Package() { 0x001fffff, 2, 0, 23 },
- Package() { 0x001fffff, 3, 0, 17 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKB, 0 },
- })
- }
-}
diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c
index 24a0efd960..6d8517ca13 100644
--- a/src/mainboard/samsung/lumpy/acpi_tables.c
+++ b/src/mainboard/samsung/lumpy/acpi_tables.c
@@ -93,24 +93,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->chromeos.vbt2 = ec_read(0xcb) ? ACTIVE_ECFW_RW : ACTIVE_ECFW_RO;
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index f1df61058b..9b0fc40de9 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -42,15 +42,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index cf2973d32a..6595f0d3dd 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -75,41 +75,7 @@ static void rcba_config(void)
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP WLAN INTA -> PIRQB
- * D28IP_P4IP ETH0 INTB -> PIRQC (MSI)
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQB
- * D31IP_SIP SATA INTA -> PIRQA (MSI)
- * D31IP_SMIP SMBUS INTC -> PIRQH
- * D31IP_TTIP THRT INTB -> PIRQG
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- *
- * LIGHTSENSOR -> PIRQE (Edge Triggered)
- * TRACKPAD -> PIRQF (Edge Triggered)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTC << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
- (INTB << D28IP_P4IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ southbridge_configure_default_intmap();
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
diff --git a/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index 2636f1320b..0000000000
--- a/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },
- Package() { 0x001cffff, 1, 0, 18 },
- Package() { 0x001cffff, 2, 0, 19 },
- Package() { 0x001cffff, 3, 0, 20 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 20 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 21 },
- Package() { 0x001fffff, 1, 0, 22 },
- Package() { 0x001fffff, 2, 0, 23 },
- Package() { 0x001fffff, 3, 0, 16 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- })
- }
-}
diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c
index 2d24822f72..dc2197a967 100644
--- a/src/mainboard/samsung/stumpy/acpi_tables.c
+++ b/src/mainboard/samsung/stumpy/acpi_tables.c
@@ -93,24 +93,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index 618d1e097d..60b112b5d1 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -33,15 +33,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 625903d3f6..2c651ae799 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -87,43 +87,7 @@ static void rcba_config(void)
{
u32 reg32;
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP WLAN INTA -> PIRQB
- * D28IP_P4IP ETH0 INTB -> PIRQC
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQE
- * D31IP_SIP SATA INTA -> PIRQF (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQG
- * D31IP_TTIP THRT INTC -> PIRQH
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
- (INTB << D28IP_P4IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
+ southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl
index e826bd6bca..79736bcafd 100644
--- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl
+++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl
@@ -343,6 +343,3 @@ Method (_CRS, 0, Serialized)
Return (MCRS)
}
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/nehalem_pci_irqs.asl"
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
index 690c072e72..427927182d 100644
--- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
@@ -378,6 +378,3 @@ Method (_CRS, 0, Serialized)
Return (MCRS)
}
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/sandybridge_pci_irqs.asl"
diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c
index 67c64d7898..902d66d0b9 100644
--- a/src/northbridge/intel/sandybridge/romstage_native.c
+++ b/src/northbridge/intel/sandybridge/romstage_native.c
@@ -91,6 +91,7 @@ void main(unsigned long bist)
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3c);
+ southbridge_configure_default_intmap();
rcba_config();
post_code(0x3d);
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 621a74341c..83de051d51 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -51,12 +51,15 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
romstage-y += early_smbus.c me_status.c gpio.c
romstage-y += reset.c
romstage-y += early_spi.c early_pch.c
+romstage-y += early_rcba.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c early_usb.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c early_usb.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c
+ramstage-y += madt.c
+
ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
diff --git a/src/southbridge/intel/bd82x6x/acpi/irq.asl b/src/southbridge/intel/bd82x6x/acpi/irq.asl
new file mode 100644
index 0000000000..61e33357e5
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/irq.asl
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* PCI Interrupt Routing */
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ /* Onboard graphics (IGD) 0:2.0 */
+ Package() { 0x0002ffff, 0, 0, 16 },/* GFX INTA -> PIRQA (MSI) */
+ /* XHCI 0:14.0 (ivy only) */
+ Package() { 0x0014ffff, 0, 0, 19 },
+ /* High Definition Audio 0:1b.0 */
+ Package() { 0x001bffff, 0, 0, 16 },/* D27IP_ZIP HDA INTA -> PIRQA (MSI) */
+ /* PCIe Root Ports 0:1c.x */
+ Package() { 0x001cffff, 0, 0, 17 },/* D28IP_P1IP PCIe INTA -> PIRQB */
+ Package() { 0x001cffff, 1, 0, 21 },/* D28IP_P2IP PCIe INTB -> PIRQF */
+ Package() { 0x001cffff, 2, 0, 19 },/* D28IP_P3IP PCIe INTC -> PIRQD */
+ Package() { 0x001cffff, 3, 0, 20 },/* D28IP_P3IP PCIe INTD -> PIRQE */
+ /* EHCI #1 0:1d.0 */
+ Package() { 0x001dffff, 0, 0, 19 },/* D29IP_E1P EHCI1 INTA -> PIRQD */
+ /* EHCI #2 0:1a.0 */
+ Package() { 0x001affff, 0, 0, 21 },/* D26IP_E2P EHCI2 INTA -> PIRQF */
+ /* LPC devices 0:1f.0 */
+ Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP SATA INTA -> PIRQB (MSI) */
+ Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP SMBUS INTB -> PIRQH */
+ Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP THRT INTC -> PIRQA */
+ Package() { 0x001fffff, 3, 0, 18 },
+ })
+ } Else {
+ Return (Package() {
+ /* Onboard graphics (IGD) 0:2.0 */
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ /* XHCI 0:14.0 (ivy only) */
+ Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ /* High Definition Audio 0:1b.0 */
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ /* PCIe Root Ports 0:1c.x */
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+ /* EHCI #1 0:1d.0 */
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ /* EHCI #2 0:1a.0 */
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ /* LPC device 0:1f.0 */
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ })
+ }
+}
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl
index 27f08e24d5..73fcfcc21d 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pch.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl
@@ -257,6 +257,8 @@ Scope(\)
// SMBus 0:1f.3
#include "smbus.asl"
+#include "irq.asl"
+
Method (_OSC, 4)
{
/* Check for XHCI */
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index d4adfd5c9f..290bb058ac 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -22,19 +22,6 @@
struct southbridge_intel_bd82x6x_config {
/**
- * Interrupt Routing configuration
- * If bit7 is 1, the interrupt is disabled.
- */
- uint8_t pirqa_routing;
- uint8_t pirqb_routing;
- uint8_t pirqc_routing;
- uint8_t pirqd_routing;
- uint8_t pirqe_routing;
- uint8_t pirqf_routing;
- uint8_t pirqg_routing;
- uint8_t pirqh_routing;
-
- /**
* GPI Routing configuration
*
* Only the lower two bits have a meaning:
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
new file mode 100644
index 0000000000..114b1749f2
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/early_rcba.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include "pch.h"
+#include "northbridge/intel/sandybridge/sandybridge.h"
+
+void
+southbridge_configure_default_intmap(void)
+{
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D28IP_P1IP SLOT1 INTA -> PIRQB
+ * D28IP_P2IP SLOT2 INTB -> PIRQF
+ * D28IP_P3IP SLOT3 INTC -> PIRQD
+ * D28IP_P5IP SLOT5 INTC -> PIRQD
+ * D29IP_E1P EHCI1 INTA -> PIRQD
+ * D26IP_E2P EHCI2 INTA -> PIRQF
+ * D31IP_SIP SATA INTA -> PIRQB (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQH
+ * D31IP_TTIP THRT INTC -> PIRQA
+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ *
+
+ */
+
+ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+ RCBA32(D30IP) = (NOINT << D30IP_PIP);
+ RCBA32(D29IP) = (INTA << D29IP_E1P);
+ RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
+ (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP);
+ RCBA32(D27IP) = (INTA << D27IP_ZIP);
+ RCBA32(D26IP) = (INTA << D26IP_E2P);
+ RCBA32(D25IP) = (NOINT << D25IP_LIP);
+ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+ /* Device interrupt route registers */
+ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+ DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+ DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
+ DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+ /* Enable IOAPIC (generic) */
+ RCBA16(OIC) = 0x0100;
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void) RCBA16(OIC);
+}
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 3c559462ee..11b765adc6 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -107,42 +107,37 @@ static void pch_enable_serial_irqs(struct device *dev)
static void pch_pirq_init(device_t dev)
{
device_t irq_dev;
- /* Get the chip configuration */
- config_t *config = dev->chip_info;
-
- pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
- pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
- pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
- pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+ /* Interrupt 11 is not used by legacy devices and so can always be used for
+ PCI interrupts. Full legacy IRQ routing is complicated and hard to
+ get right. Fortunately all modern OS use MSI and so it's not that big of
+ an issue anyway. Still we have to provide a reasonable default. Using
+ interrupt 11 for it everywhere is a working default. ACPI-aware OS can
+ move it to any interrupt and others will just leave them at default.
+ */
+ const u8 pirq_routing = 11;
- pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
- pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
- pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
- pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+ pci_write_config8(dev, PIRQA_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQB_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQC_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQD_ROUT, pirq_routing);
- /* Eric Biederman once said we should let the OS do this.
- * I am not so sure anymore he was right.
- */
+ pci_write_config8(dev, PIRQE_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQF_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin=0, int_line=0;
+ u8 int_pin=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
- switch (int_pin) {
- case 1: /* INTA# */ int_line = config->pirqa_routing; break;
- case 2: /* INTB# */ int_line = config->pirqb_routing; break;
- case 3: /* INTC# */ int_line = config->pirqc_routing; break;
- case 4: /* INTD# */ int_line = config->pirqd_routing; break;
- }
-
- if (!int_line)
+ if (int_pin == 0)
continue;
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, pirq_routing);
}
}
diff --git a/src/southbridge/intel/bd82x6x/madt.c b/src/southbridge/intel/bd82x6x/madt.c
new file mode 100644
index 0000000000..45b652bd61
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/madt.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 9b84c6706f..7cde7bc9c9 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -75,6 +75,7 @@ void enable_usb_bar(void);
int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read(u32 offset, u32 size, u8 *buffer);
void early_thermal_init(void);
+void southbridge_configure_default_intmap(void);
void early_pch_init_native(void);
int southbridge_detect_s3_resume(void);
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 2db758a056..cfcba5429d 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -43,6 +43,7 @@ ramstage-y += ../bd82x6x/watchdog.c
ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
ramstage-y += ../common/spi.c
+ramstage-y += madt.c
smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
@@ -50,6 +51,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x
romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c early_thermal.c
romstage-y += ../bd82x6x/reset.c
+romstage-y += ../bd82x6x/early_rcba.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 03b40495e1..212471136d 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -106,42 +106,37 @@ static void pch_enable_serial_irqs(struct device *dev)
static void pch_pirq_init(device_t dev)
{
device_t irq_dev;
- /* Get the chip configuration */
- config_t *config = dev->chip_info;
-
- pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
- pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
- pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
- pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+ /* Interrupt 11 is not used by legacy devices and so can always be used for
+ PCI interrupts. Full legacy IRQ routing is complicated and hard to
+ get right. Fortunately all modern OS use MSI and so it's not that big of
+ an issue anyway. Still we have to provide a reasonable default. Using
+ interrupt 11 for it everywhere is a working default. ACPI-aware OS can
+ move it to any interrupt and others will just leave them at default.
+ */
+ const u8 pirq_routing = 11;
- pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
- pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
- pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
- pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+ pci_write_config8(dev, PIRQA_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQB_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQC_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQD_ROUT, pirq_routing);
- /* Eric Biederman once said we should let the OS do this.
- * I am not so sure anymore he was right.
- */
+ pci_write_config8(dev, PIRQE_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQF_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin=0, int_line=0;
+ u8 int_pin=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
- switch (int_pin) {
- case 1: /* INTA# */ int_line = config->pirqa_routing; break;
- case 2: /* INTB# */ int_line = config->pirqb_routing; break;
- case 3: /* INTC# */ int_line = config->pirqc_routing; break;
- case 4: /* INTD# */ int_line = config->pirqd_routing; break;
- }
-
- if (!int_line)
+ if (int_pin == 0)
continue;
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, pirq_routing);
}
}
diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c
new file mode 100644
index 0000000000..69a7b4b65b
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/madt.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 1, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2,
+ MP_IRQ_POLARITY_DEFAULT |
+ MP_IRQ_TRIGGER_DEFAULT);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9,
+ MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_LEVEL);
+
+ /* LAPIC_NMI */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 0,
+ MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 1, MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 2, MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 3, MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ return current;
+}
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index df125f052d..bd94689e78 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -79,6 +79,7 @@ int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
int early_spi_read(u32 offset, u32 size, u8 *buffer);
void early_thermal_init(void);
+void southbridge_configure_default_intmap(void);
#endif
#endif