diff options
| -rw-r--r-- | payloads/libpayload/include/armv7/arch/cache.h | 15 | ||||
| -rw-r--r-- | src/arch/armv7/include/arch/cache.h | 15 |
2 files changed, 30 insertions, 0 deletions
diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/payloads/libpayload/include/armv7/arch/cache.h index 2928d10017..0414da37f2 100644 --- a/payloads/libpayload/include/armv7/arch/cache.h +++ b/payloads/libpayload/include/armv7/arch/cache.h @@ -240,6 +240,21 @@ static inline void write_l2ctlr(uint32_t val) isb(); } +/* read L2 Auxiliary Control Register (L2ACTLR) */ +static inline uint32_t read_l2actlr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); + return val; +} + +/* write L2 Auxiliary Control Register (L2ACTLR) */ +static inline void write_l2actlr(uint32_t val) +{ + asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" ); + isb(); +} + /* read system control register (SCTLR) */ static inline uint32_t read_sctlr(void) { diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 5166af3f9b..8a14ff9388 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -246,6 +246,21 @@ static inline void write_l2ctlr(uint32_t val) isb(); } +/* read L2 Auxiliary Control Register (L2ACTLR) */ +static inline uint32_t read_l2actlr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); + return val; +} + +/* write L2 Auxiliary Control Register (L2ACTLR) */ +static inline void write_l2actlr(uint32_t val) +{ + asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" ); + isb(); +} + /* read system control register (SCTLR) */ static inline uint32_t read_sctlr(void) { |